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Sun, 30 Jun 2019 22:30:05 -0700 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1hhot6-0003EO-Ie; Sun, 30 Jun 2019 22:30:00 -0700 Received: from xsj-pvapsmtp01 (smtp2.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id x615Tuah023632; Sun, 30 Jun 2019 22:29:56 -0700 Received: from [172.23.64.106] (helo=xhdvnc125.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1hhot2-0003Cd-4S; Sun, 30 Jun 2019 22:29:56 -0700 Received: by xhdvnc125.xilinx.com (Postfix, from userid 16987) id 4D3BC12174A; Mon, 1 Jul 2019 10:59:54 +0530 (IST) From: Manish Narani To: ulf.hansson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, heiko@sntech.de, michal.simek@xilinx.com, adrian.hunter@intel.com, christoph.muellner@theobroma-systems.com, philipp.tomsich@theobroma-systems.com, viresh.kumar@linaro.org, scott.branden@broadcom.com, ayaka@soulik.info, kernel@esmil.dk, tony.xie@rock-chips.com, rajan.vaja@xilinx.com, jolly.shah@xilinx.com, nava.manne@xilinx.com, mdf@kernel.org, manish.narani@xilinx.com, olof@lixom.net Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH v2 07/11] dt-bindings: mmc: arasan: Add optional properties for Arasan SDHCI Date: Mon, 1 Jul 2019 10:59:47 +0530 Message-Id: <1561958991-21935-8-git-send-email-manish.narani@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1561958991-21935-1-git-send-email-manish.narani@xilinx.com> References: <1561958991-21935-1-git-send-email-manish.narani@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.100;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(4636009)(136003)(346002)(376002)(39860400002)(396003)(2980300002)(199004)(189003)(47776003)(8936002)(76176011)(26005)(336012)(5660300002)(51416003)(36756003)(70586007)(70206006)(186003)(356004)(6666004)(106002)(6266002)(7416002)(42186006)(16586007)(316002)(72206003)(44832011)(478600001)(48376002)(63266004)(36386004)(52956003)(2906002)(50466002)(103686004)(50226002)(305945005)(81166006)(81156014)(8676002)(4326008)(426003)(446003)(11346002)(2616005)(476003)(126002)(486006)(921003)(1121003)(5001870100001);DIR:OUT;SFP:1101;SCL:1;SRVR:DM6PR02MB5241;H:xsj-pvapsmtpgw02;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-100.xilinx.com,xapps1.xilinx.com;A:1;MX:1; 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Signed-off-by: Manish Narani --- Documentation/devicetree/bindings/mmc/arasan,sdhci.txt | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt index 7c79496..7425d52 100644 --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt @@ -49,6 +49,21 @@ Optional Properties: properly. Test mode can be used to force the controller to function. - xlnx,int-clock-stable-broken: when present, the controller always reports that the internal clock is stable even when it is not. + - clk-phase-legacy: Input/Output Clock Delay pair in degrees for Legacy Mode. + - clk-phase-mmc-hs: Input/Output Clock Delay pair degrees for MMC HS. + - clk-phase-sd-hs: Input/Output Clock Delay pair in degrees for SD HS. + - clk-phase-uhs-sdr12: Input/Output Clock Delay pair in degrees for SDR12. + - clk-phase-uhs-sdr25: Input/Output Clock Delay pair in degrees for SDR25. + - clk-phase-uhs-sdr50: Input/Output Clock Delay pair in degrees for SDR50. + - clk-phase-uhs-sdr104: Input/Output Clock Delay pair in degrees for SDR104. + - clk-phase-uhs-ddr50: Input/Output Clock Delay pair in degrees for SD DDR50. + - clk-phase-mmc-ddr52: Input/Output Clock Delay pair in degrees for MMC DDR52. + - clk-phase-mmc-hs200: Input/Output Clock Delay pair in degrees for MMC HS200. + - clk-phase-mmc-hs400: Input/Output Clock Delay pair in degrees for MMC HS400. + + Above mentioned are the clock (phase) delays which are to be configured in the + controller while switching to particular speed mode. If not specified, driver + will configure the default value defined for particular mode in it. Example: sdhci@e0100000 {