| Message ID | 20190701062632.456-5-animesh.manna@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | DSB enablement. | expand |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7e6009cefb18..b2e8349f3295 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -178,11 +178,22 @@ */ #define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val)) +/* + * Added enum to hold the capability for those registers which can be written + * through DSB. + */ +enum reg_write_cap { + MMIO_WRITE, + DSB_WRITE, + DSB_INDEX_WRITE +}; + typedef struct { u32 reg; + enum reg_write_cap cap; } i915_reg_t; -#define _MMIO(r) ((const i915_reg_t){ .reg = (r) }) +#define _MMIO(r, ...) ((const i915_reg_t){ .reg = (r), ##__VA_ARGS__}) #define INVALID_MMIO_REG _MMIO(0)
DSB can access specific register, To identify those register which can be written through DSB, enum reg_write_cap is added to hold the capability. Cc: Jani Nikula <jani.nikula@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-)