diff mbox series

[next] drm/amdgpu/psp: fix incorrect logic when checking asic_type

Message ID 20190704142329.22983-1-colin.king@canonical.com (mailing list archive)
State New, archived
Headers show
Series [next] drm/amdgpu/psp: fix incorrect logic when checking asic_type | expand

Commit Message

Colin King July 4, 2019, 2:23 p.m. UTC 
From: Colin Ian King <colin.king@canonical.com>

Currently the check of the asic_type is always returning true because
of the use of ||.  Fix this by using && instead.  Also break overly
wide line.

Addresses-Coverity: ("Constant expression result")
Fixes: dab70ff24db6 ("drm/amdgpu/psp: add psp support for navi14")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
---
 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Comments

Walter Harms July 4, 2019, 4:22 p.m. UTC | #1 
Am 04.07.2019 16:23, schrieb Colin King:
> From: Colin Ian King <colin.king@canonical.com>
> 
> Currently the check of the asic_type is always returning true because
> of the use of ||.  Fix this by using && instead.  Also break overly
> wide line.
> 
> Addresses-Coverity: ("Constant expression result")
> Fixes: dab70ff24db6 ("drm/amdgpu/psp: add psp support for navi14")
> Signed-off-by: Colin Ian King <colin.king@canonical.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> index 527dc371598d..e4afd34e3034 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> @@ -540,7 +540,8 @@ psp_v11_0_sram_map(struct amdgpu_device *adev,
>  
>  	case AMDGPU_UCODE_ID_RLC_G:
>  		*sram_offset = 0x2000;
> -		if (adev->asic_type != CHIP_NAVI10 || adev->asic_type != CHIP_NAVI14) {
> +		if (adev->asic_type != CHIP_NAVI10 &&
> +		    adev->asic_type != CHIP_NAVI14) {
>  			*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
>  			*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
>  		} else {
> @@ -551,7 +552,8 @@ psp_v11_0_sram_map(struct amdgpu_device *adev,
>  
>  	case AMDGPU_UCODE_ID_SDMA0:
>  		*sram_offset = 0x0;
> -		if (adev->asic_type != CHIP_NAVI10 || adev->asic_type != CHIP_NAVI14) {
> +		if (adev->asic_type != CHIP_NAVI10 &&
> +		    adev->asic_type != CHIP_NAVI14) {
>  			*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
>  			*sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
>  		} else {


maybe it is better to use
		if (adev->asic_type == CHIP_NAVI10 ||
		    adev->asic_type == CHIP_NAVI14) {

i guess tha was intended here and it is more easy to read.
ppl are bad in non-non reading.

re,
 wh
Colin King July 4, 2019, 4:26 p.m. UTC | #2 
On 04/07/2019 17:22, walter harms wrote:
> 
> 
> Am 04.07.2019 16:23, schrieb Colin King:
>> From: Colin Ian King <colin.king@canonical.com>
>>
>> Currently the check of the asic_type is always returning true because
>> of the use of ||.  Fix this by using && instead.  Also break overly
>> wide line.
>>
>> Addresses-Coverity: ("Constant expression result")
>> Fixes: dab70ff24db6 ("drm/amdgpu/psp: add psp support for navi14")
>> Signed-off-by: Colin Ian King <colin.king@canonical.com>
>> ---
>>  drivers/gpu/drm/amd/amdgpu/psp_v11_0.c | 6 ++++--
>>  1 file changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
>> index 527dc371598d..e4afd34e3034 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
>> @@ -540,7 +540,8 @@ psp_v11_0_sram_map(struct amdgpu_device *adev,
>>  
>>  	case AMDGPU_UCODE_ID_RLC_G:
>>  		*sram_offset = 0x2000;
>> -		if (adev->asic_type != CHIP_NAVI10 || adev->asic_type != CHIP_NAVI14) {
>> +		if (adev->asic_type != CHIP_NAVI10 &&
>> +		    adev->asic_type != CHIP_NAVI14) {
>>  			*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
>>  			*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
>>  		} else {
>> @@ -551,7 +552,8 @@ psp_v11_0_sram_map(struct amdgpu_device *adev,
>>  
>>  	case AMDGPU_UCODE_ID_SDMA0:
>>  		*sram_offset = 0x0;
>> -		if (adev->asic_type != CHIP_NAVI10 || adev->asic_type != CHIP_NAVI14) {
>> +		if (adev->asic_type != CHIP_NAVI10 &&
>> +		    adev->asic_type != CHIP_NAVI14) {
>>  			*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
>>  			*sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
>>  		} else {
> 
> 
> maybe it is better to use
> 		if (adev->asic_type == CHIP_NAVI10 ||
> 		    adev->asic_type == CHIP_NAVI14) {
> 
> i guess tha was intended here and it is more easy to read.
> ppl are bad in non-non reading.

I'm not sure what the original intent was now.  Lets see what the folk
at AMD say about this.

> 
> re,
>  wh
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 527dc371598d..e4afd34e3034 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -540,7 +540,8 @@  psp_v11_0_sram_map(struct amdgpu_device *adev,
 
 	case AMDGPU_UCODE_ID_RLC_G:
 		*sram_offset = 0x2000;
-		if (adev->asic_type != CHIP_NAVI10 || adev->asic_type != CHIP_NAVI14) {
+		if (adev->asic_type != CHIP_NAVI10 &&
+		    adev->asic_type != CHIP_NAVI14) {
 			*sram_addr_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_ADDR);
 			*sram_data_reg_offset = SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UCODE_DATA);
 		} else {
@@ -551,7 +552,8 @@  psp_v11_0_sram_map(struct amdgpu_device *adev,
 
 	case AMDGPU_UCODE_ID_SDMA0:
 		*sram_offset = 0x0;
-		if (adev->asic_type != CHIP_NAVI10 || adev->asic_type != CHIP_NAVI14) {
+		if (adev->asic_type != CHIP_NAVI10 &&
+		    adev->asic_type != CHIP_NAVI14) {
 			*sram_addr_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_ADDR);
 			*sram_data_reg_offset = SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_UCODE_DATA);
 		} else {