@@ -68,6 +68,8 @@
* @domain: irq domain for this interrupt controller
* @lock: mutex to serialize access to INTC
* @host_mask: indicate which HOST IRQs are enabled
+ * @shared_intr: bit-map denoting if the MPU host interrupt is shared
+ * @invalid_intr: bit-map denoting if host interrupt is connected to MPU
*/
struct pruss_intc {
unsigned int irqs[MAX_NUM_HOST_IRQS];
@@ -76,6 +78,8 @@ struct pruss_intc {
struct irq_domain *domain;
struct mutex lock; /* PRUSS INTC lock */
u32 host_mask;
+ u16 shared_intr;
+ u16 invalid_intr;
};
static inline u32 pruss_intc_read_reg(struct pruss_intc *intc, unsigned int reg)
@@ -243,7 +247,8 @@ static int pruss_intc_probe(struct platform_device *pdev)
struct pruss_intc *intc;
struct resource *res;
struct irq_chip *irqchip;
- int i, irq;
+ int i, irq, count;
+ u8 temp_intr[MAX_NUM_HOST_IRQS] = { 0 };
intc = devm_kzalloc(dev, sizeof(*intc), GFP_KERNEL);
if (!intc)
@@ -260,6 +265,39 @@ static int pruss_intc_probe(struct platform_device *pdev)
dev_dbg(dev, "intc memory: pa %pa size 0x%zx va %pK\n", &res->start,
(size_t)resource_size(res), intc->base);
+ count = of_property_read_variable_u8_array(dev->of_node,
+ "ti,irqs-reserved",
+ temp_intr, 0,
+ MAX_NUM_HOST_IRQS);
+ if (count < 0 && count != -EINVAL)
+ return count;
+ count = (count == -EINVAL ? 0 : count);
+ for (i = 0; i < count; i++) {
+ if (temp_intr[i] < MAX_NUM_HOST_IRQS) {
+ intc->invalid_intr |= BIT(temp_intr[i]);
+ } else {
+ dev_warn(dev, "ignoring invalid reserved irq %d\n",
+ temp_intr[i]);
+ }
+ temp_intr[i] = 0;
+ }
+
+ count = of_property_read_variable_u8_array(dev->of_node,
+ "ti,irqs-shared",
+ temp_intr, 0,
+ MAX_NUM_HOST_IRQS);
+ if (count < 0 && count != -EINVAL)
+ return count;
+ count = (count == -EINVAL ? 0 : count);
+ for (i = 0; i < count; i++) {
+ if (temp_intr[i] < MAX_NUM_HOST_IRQS) {
+ intc->shared_intr |= BIT(temp_intr[i]);
+ } else {
+ dev_warn(dev, "ignoring invalid reserved irq %d\n",
+ temp_intr[i]);
+ }
+ }
+
mutex_init(&intc->lock);
pruss_intc_init(intc);
@@ -286,6 +324,10 @@ static int pruss_intc_probe(struct platform_device *pdev)
for (i = 0; i < MAX_NUM_HOST_IRQS; i++) {
irq = platform_get_irq_byname(pdev, irq_names[i]);
if (irq < 0) {
+ if (intc->shared_intr & BIT(i) ||
+ intc->invalid_intr & BIT(i))
+ continue;
+
dev_err(dev->parent, "platform_get_irq_byname failed for %s : %d\n",
irq_names[i], irq);
goto fail_irq;
The PRUSS INTC has a fixed number of output interrupt lines that are connected to a number of processors or other PRUSS instances or other devices (like DMA) on the SoC. The output interrupt lines 2 through 9 are usually connected to the main ARM host processor and are referred to as host interrupts 0 through 7 from ARM/MPU perspective. All of these 8 host interrupts are not always exclusively connected to the ARM GIC. Some SoCs have some interrupt lines not connected to the ARM GIC at all, while a few others have the interrupt lines connected to multiple processors in which they need to be partitioned as per SoC integration needs. For example, AM437x and 66AK2G SoCs have 2 PRUSS instances each and have the host interrupt 5 connected to the other PRUSS, while AM335x has host interrupt 0 shared between MPU and TSC_ADC and host interrupts 6 & 7 shared between MPU and a DMA controller. Add support to the PRUSS INTC driver to allow both these shared and invalid interrupts by not returning a failure if any of these interrupts are skipped from the corresponding INTC DT node. Signed-off-by: Suman Anna <s-anna@ti.com> --- drivers/irqchip/irq-pruss-intc.c | 44 +++++++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-)