| Message ID | 20190708125325.16576-6-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Plane cdclk requirements and fp16 for gen4+ | expand |
Op 08-07-2019 om 14:53 schreef Ville Syrjala: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Bspec says that glk+ max downscale factor is <3.0 for all pixel formats. > Older platforms had a max of <2.0 for NV12. Update the code to deal with > this. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index ee93577bdf95..2b8a6a84605c 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -14472,7 +14472,7 @@ skl_max_scale(const struct intel_crtc_state *crtc_state, > { > struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > - int max_scale, mult; > + int max_scale; > int crtc_clock, max_dotclk, tmpclk1, tmpclk2; > > if (!crtc_state->base.enable) > @@ -14493,8 +14493,11 @@ skl_max_scale(const struct intel_crtc_state *crtc_state, > * or > * cdclk/crtc_clock > */ > - mult = drm_format_info_is_yuv_semiplanar(format) ? 2 : 3; > - tmpclk1 = (1 << 16) * mult - 1; > + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) || > + !drm_format_info_is_yuv_semiplanar(format)) > + tmpclk1 = 0x30000 - 1; > + else > + tmpclk1 = 0x20000 - 1; > tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock); > max_scale = min(tmpclk1, tmpclk2); > For this patch and 4, 6, 7, 8: Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Patch 4 seems to be exactly the same as the patch I wrote for it, so lets upstream this ASAP before someone else does as well. ;)
On Wed, Sep 11, 2019 at 11:53:54AM +0200, Maarten Lankhorst wrote: > Op 08-07-2019 om 14:53 schreef Ville Syrjala: > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > Bspec says that glk+ max downscale factor is <3.0 for all pixel formats. > > Older platforms had a max of <2.0 for NV12. Update the code to deal with > > this. > > > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 9 ++++++--- > > 1 file changed, 6 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > index ee93577bdf95..2b8a6a84605c 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -14472,7 +14472,7 @@ skl_max_scale(const struct intel_crtc_state *crtc_state, > > { > > struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > - int max_scale, mult; > > + int max_scale; > > int crtc_clock, max_dotclk, tmpclk1, tmpclk2; > > > > if (!crtc_state->base.enable) > > @@ -14493,8 +14493,11 @@ skl_max_scale(const struct intel_crtc_state *crtc_state, > > * or > > * cdclk/crtc_clock > > */ > > - mult = drm_format_info_is_yuv_semiplanar(format) ? 2 : 3; > > - tmpclk1 = (1 << 16) * mult - 1; > > + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) || > > + !drm_format_info_is_yuv_semiplanar(format)) > > + tmpclk1 = 0x30000 - 1; > > + else > > + tmpclk1 = 0x20000 - 1; > > tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock); > > max_scale = min(tmpclk1, tmpclk2); > > > > For this patch and 4, 6, 7, 8: > > Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > > Patch 4 seems to be exactly the same as the patch I wrote for it, so lets upstream this ASAP before someone else does as well. ;) Almost the same, except the 'if (fourcc && ...)' part in the readout. IIRC otherwise it would WARN when we try to look up the format info w/ fourcc==0. Thanks for the review.
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ee93577bdf95..2b8a6a84605c 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -14472,7 +14472,7 @@ skl_max_scale(const struct intel_crtc_state *crtc_state, { struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - int max_scale, mult; + int max_scale; int crtc_clock, max_dotclk, tmpclk1, tmpclk2; if (!crtc_state->base.enable) @@ -14493,8 +14493,11 @@ skl_max_scale(const struct intel_crtc_state *crtc_state, * or * cdclk/crtc_clock */ - mult = drm_format_info_is_yuv_semiplanar(format) ? 2 : 3; - tmpclk1 = (1 << 16) * mult - 1; + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) || + !drm_format_info_is_yuv_semiplanar(format)) + tmpclk1 = 0x30000 - 1; + else + tmpclk1 = 0x20000 - 1; tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock); max_scale = min(tmpclk1, tmpclk2);