| Message ID | 20190710063056.35689-3-Anson.Huang@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [V5,1/5] clocksource: imx-sysctr: Add internal clock divider handle | expand |
On Wed, Jul 10, 2019 at 02:30:54PM +0800, Anson.Huang@nxp.com wrote: > From: Anson Huang <Anson.Huang@nxp.com> > > Add i.MX8MM system counter node to enable timer-imx-sysctr > broadcast timer driver. > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Do I need to wait for patch #1 landing before I apply #3 ~ #5, or can they be applied independently (no breaking on anything)? Shawn > --- > Changes since V4: > - update the clock info using fixed clock node; > - correct the reg range; > - update the interrupt number as the system counter driver ONLY uses 1 irq now. > --- > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > index b5637f8..8cf7f34 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > @@ -560,6 +560,14 @@ > #pwm-cells = <2>; > status = "disabled"; > }; > + > + system_counter: timer@306a0000 { > + compatible = "nxp,sysctr-timer"; > + reg = <0x306a0000 0x20000>; > + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&osc_24m>; > + clock-names = "per"; > + }; > }; > > aips3: bus@30800000 { > -- > 2.7.4 >
Hi, Shawn > On Wed, Jul 10, 2019 at 02:30:54PM +0800, Anson.Huang@nxp.com wrote: > > From: Anson Huang <Anson.Huang@nxp.com> > > > > Add i.MX8MM system counter node to enable timer-imx-sysctr broadcast > > timer driver. > > > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > > Do I need to wait for patch #1 landing before I apply #3 ~ #5, or can they be > applied independently (no breaking on anything)? Without #1, system can bootup, but the system counter's freq will be incorrect, although it does NOT impact normal function. So I think it is better to wait for #1 landing. @daniel.lezcano@linaro.org, can you help review the #1 patch, since I use a different way to fix the clock issue which is more simple. Anson
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index b5637f8..8cf7f34 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -560,6 +560,14 @@ #pwm-cells = <2>; status = "disabled"; }; + + system_counter: timer@306a0000 { + compatible = "nxp,sysctr-timer"; + reg = <0x306a0000 0x20000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc_24m>; + clock-names = "per"; + }; }; aips3: bus@30800000 {