From patchwork Wed Jul 10 18:37:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Janakarajan Natarajan X-Patchwork-Id: 11038809 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0704D112C for ; Wed, 10 Jul 2019 18:37:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id ECB70289E8 for ; Wed, 10 Jul 2019 18:37:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DF83A289DC; Wed, 10 Jul 2019 18:37:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3C1E2284DC for ; Wed, 10 Jul 2019 18:37:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728369AbfGJShg (ORCPT ); Wed, 10 Jul 2019 14:37:36 -0400 Received: from mail-eopbgr740044.outbound.protection.outlook.com ([40.107.74.44]:2304 "EHLO NAM01-BN3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1728313AbfGJShX (ORCPT ); Wed, 10 Jul 2019 14:37:23 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=c8ioBU9PAAqJNA9ahES7jO0iNWd7rat9aN50Rsi2OtI=; b=gp/yoUtNS021+2qiPQ8zd6/6sl+QHHbGvtqsvyIrU3b5gIfgM/pBv25YWVgSy/nvMVcJb2I6Xa2ZvxG2o1W8cVJKUgGy4CskwW4/Fcd2As/CtrC4L40KXpyhFF1kfCjH6Y0ncqY+7vsfXt4Igmnqr22nd/yxZpXM2Zt5OB8o5LA= Received: from SN6PR12MB2736.namprd12.prod.outlook.com (52.135.107.27) by SN6PR12MB2749.namprd12.prod.outlook.com (52.135.107.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2052.19; Wed, 10 Jul 2019 18:37:20 +0000 Received: from SN6PR12MB2736.namprd12.prod.outlook.com ([fe80::a475:e612:8e1e:ed28]) by SN6PR12MB2736.namprd12.prod.outlook.com ([fe80::a475:e612:8e1e:ed28%3]) with mapi id 15.20.2052.020; Wed, 10 Jul 2019 18:37:20 +0000 From: "Natarajan, Janakarajan" To: "linux-acpi@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-pm@vger.kernel.org" , "devel@acpica.org" CC: "Rafael J . Wysocki" , Len Brown , Viresh Kumar , Robert Moore , Erik Schmauss , "Ghannam, Yazen" , "Ghannam, Yazen" , "Natarajan, Janakarajan" Subject: [PATCHv3 5/6] acpi/cppc: Add support for CPPC Enable register Thread-Topic: [PATCHv3 5/6] acpi/cppc: Add support for CPPC Enable register Thread-Index: AQHVN06A9flMOYmKH0yRLd2nLrnssw== Date: Wed, 10 Jul 2019 18:37:17 +0000 Message-ID: <40c32db191fa023f7f8f1e48d58565a22b8fcbd6.1562781484.git.Janakarajan.Natarajan@amd.com> References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: SN4PR0201CA0064.namprd02.prod.outlook.com (2603:10b6:803:20::26) To SN6PR12MB2736.namprd12.prod.outlook.com (2603:10b6:805:77::27) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Janakarajan.Natarajan@amd.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [165.204.78.2] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: d0749c57-ff40-4eae-c3bb-08d70565a249 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020);SRVR:SN6PR12MB2749; x-ms-traffictypediagnostic: SN6PR12MB2749: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:8273; x-forefront-prvs: 0094E3478A x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(4636009)(366004)(136003)(376002)(346002)(396003)(39860400002)(199004)(189003)(66476007)(66946007)(5660300002)(66556008)(81166006)(2906002)(54906003)(64756008)(50226002)(36756003)(186003)(6486002)(6506007)(386003)(316002)(110136005)(102836004)(2501003)(14454004)(8936002)(68736007)(66446008)(2201001)(99286004)(7736002)(446003)(478600001)(118296001)(305945005)(52116002)(53936002)(76176011)(6512007)(8676002)(86362001)(256004)(11346002)(486006)(25786009)(14444005)(476003)(2616005)(3846002)(6436002)(26005)(6116002)(71200400001)(71190400001)(81156014)(6666004)(4326008)(66066001);DIR:OUT;SFP:1101;SCL:1;SRVR:SN6PR12MB2749;H:SN6PR12MB2736.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: PXxgfJXmR4zEpUVENmUVVCP5kW1ZM6VWbFYkECRBjD27EkNYi7KkMcMTiJ2b5ufhKKXVAfcdf3LAZxzz2WEZgwjOCI9R1yUJqL8T1PQN1iO8Xkgv4ZlpwJeqvbLjgzX/bZdii5Y8j+KPCOiCLRJnM/tx60v3e3hgWbniH+qQNHBfW0AeA2WKj8lcNkwThu4OUeYQ2jBjw6HTUgVk8qFBQrn/MXf0iNxJBxQSSOIrnKHlNqmvrEawqYDqUoKWMbcdruI3eOcVwXIQz+P3mVXwqSc+301NmtTAHQ9dGxVL2K3QxmRI3Xu0LhdzlOdmqEw6VVa6JhR1QTIho+cYZYRuZ/dWoFpE2Uin069PB2yDvCqGCHA3qD8c8JpclyKet6V8X7YZwMSiKs3f8Ost2fHpo6af1LZSu0H/HJ9zBHTAblU= MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: d0749c57-ff40-4eae-c3bb-08d70565a249 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Jul 2019 18:37:17.5259 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jnataraj@amd.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR12MB2749 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Yazen Ghannam To enable CPPC on a processor, the OS should write a value "1" to the CPPC Enable register. Add support for this register. Since we have a new variable "enable" in cppc_perf_ctrls, rename it and the associated functions i.e. cppc_perf_ctrls->cppc_ctrls and cppc_get_perf()->cppc_get_ctrls(). Signed-off-by: Yazen Ghannam [ carved out into a patch, cleaned up, productized ] Signed-off-by: Janakarajan Natarajan --- drivers/acpi/cppc_acpi.c | 44 ++++++++++++++++++++++++---------------- include/acpi/cppc_acpi.h | 10 +++++---- 2 files changed, 33 insertions(+), 21 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index b24e54263efb..3199433e3f71 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1343,12 +1343,12 @@ EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs); /** * cppc_set_reg - Set the CPUs control register. * @cpu: CPU for which to set the register. - * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h + * @ctrls: ptr to cppc_ctrls. See cppc_acpi.h * @reg_idx: Index of the register being accessed * * Return: 0 for success, -ERRNO otherwise. */ -int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, +int cppc_set_reg(int cpu, struct cppc_ctrls *ctrls, enum cppc_regs reg_idx) { struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); @@ -1364,20 +1364,23 @@ int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, } switch (reg_idx) { + case ENABLE: + value = ctrls->enable; + break; case DESIRED_PERF: - value = perf_ctrls->desired_perf; + value = ctrls->desired_perf; break; case MAX_PERF: - value = perf_ctrls->max_perf; + value = ctrls->max_perf; break; case MIN_PERF: - value = perf_ctrls->min_perf; + value = ctrls->min_perf; break; case ENERGY_PERF: - value = perf_ctrls->energy_perf; + value = ctrls->energy_perf; break; case AUTO_SEL_ENABLE: - value = perf_ctrls->auto_sel_enable; + value = ctrls->auto_sel_enable; break; default: pr_debug("CPC register index #%d not writeable\n", reg_idx); @@ -1485,13 +1488,14 @@ int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, } EXPORT_SYMBOL_GPL(cppc_set_reg); -int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) +int cppc_get_ctrls(int cpu, struct cppc_ctrls *ctrls) { struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); struct cpc_register_resource *desired_reg, *max_reg, *min_reg; struct cpc_register_resource *energy_reg, *auto_sel_enable_reg; + struct cpc_register_resource *enable_reg; int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); - u64 desired, max, min, energy, auto_sel_enable; + u64 desired, max, min, energy, auto_sel_enable, enable; struct cppc_pcc_data *pcc_ss_data = NULL; int ret = 0, regs_in_pcc = 0; @@ -1500,6 +1504,7 @@ int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) return -ENODEV; } + enable_reg = &cpc_desc->cpc_regs[ENABLE]; desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF]; max_reg = &cpc_desc->cpc_regs[MAX_PERF]; min_reg = &cpc_desc->cpc_regs[MIN_PERF]; @@ -1509,7 +1514,7 @@ int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) /* Check if any of the perf registers are in PCC */ if (CPC_IN_PCC(desired_reg) || CPC_IN_PCC(max_reg) || CPC_IN_PCC(min_reg) || CPC_IN_PCC(energy_reg) || - CPC_IN_PCC(auto_sel_enable_reg)) { + CPC_IN_PCC(auto_sel_enable_reg) || CPC_IN_PCC(enable_reg)) { pcc_ss_data = pcc_data[pcc_ss_id]; down_write(&pcc_ss_data->pcc_lock); regs_in_pcc = 1; @@ -1521,10 +1526,14 @@ int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) } } - /* desired_perf is the only mandatory value in perf_ctrls */ + /* desired_perf is the only mandatory value in ctrls */ if (cpc_read(cpu, desired_reg, &desired)) ret = -EFAULT; + if (CPC_SUP_BUFFER_ONLY(enable_reg) && + cpc_read(cpu, enable_reg, &enable)) + ret = -EFAULT; + if (CPC_SUP_BUFFER_ONLY(max_reg) && cpc_read(cpu, max_reg, &max)) ret = -EFAULT; @@ -1540,11 +1549,12 @@ int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) ret = -EFAULT; if (!ret) { - perf_ctrls->desired_perf = desired; - perf_ctrls->max_perf = max; - perf_ctrls->min_perf = min; - perf_ctrls->energy_perf = energy; - perf_ctrls->auto_sel_enable = auto_sel_enable; + ctrls->enable = enable; + ctrls->desired_perf = desired; + ctrls->max_perf = max; + ctrls->min_perf = min; + ctrls->energy_perf = energy; + ctrls->auto_sel_enable = auto_sel_enable; } out_err: @@ -1552,7 +1562,7 @@ int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) up_write(&pcc_ss_data->pcc_lock); return ret; } -EXPORT_SYMBOL_GPL(cppc_get_perf); +EXPORT_SYMBOL_GPL(cppc_get_ctrls); /** * cppc_get_transition_latency - returns frequency transition latency in ns diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index 80720b246c51..e6cd2a487874 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -109,7 +109,8 @@ struct cppc_perf_caps { u32 nominal_freq; }; -struct cppc_perf_ctrls { +struct cppc_ctrls { + bool enable; u32 max_perf; u32 min_perf; u32 desired_perf; @@ -128,17 +129,18 @@ struct cppc_perf_fb_ctrs { struct cppc_cpudata { int cpu; struct cppc_perf_caps perf_caps; - struct cppc_perf_ctrls perf_ctrls; + struct cppc_ctrls ctrls; struct cppc_perf_fb_ctrs perf_fb_ctrs; struct cpufreq_policy *cur_policy; unsigned int shared_type; cpumask_var_t shared_cpu_map; }; +extern int cppc_get_enable(int cpu); extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf); extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs); -extern int cppc_set_reg(int cpu, struct cppc_perf_ctrls *perf_ctrls, enum cppc_regs reg_idx); -extern int cppc_get_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); +extern int cppc_set_reg(int cpu, struct cppc_ctrls *ctrls, enum cppc_regs reg_idx); +extern int cppc_get_ctrls(int cpu, struct cppc_ctrls *ctrls); extern int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps); extern int acpi_get_psd_map(struct cppc_cpudata **); extern unsigned int cppc_get_transition_latency(int cpu);