[kvm-unit-tests,v2,1/3] tscdeadline_latency: Check condition first before loop
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Message ID 20190712022825.1366-2-peterx@redhat.com
State New
Headers show
Series
  • tscdeadline_latency: Some fixes of hangs
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Commit Message

Peter Xu July 12, 2019, 2:28 a.m. UTC
This patch fixes a tscdeadline_latency hang when specifying a very
small breakmax value.  It's easily reproduced on my host when set
breakmax to e.g. 10 TSC clocks.

The problem is test_tsc_deadline_timer() can be very slow because
we've got printf() in there.  So when reach the main loop we might
have already triggered the IRQ handler for multiple times and we might
have triggered the hitmax condition which will turn IRQ off.  Then
with no IRQ that first HLT instruction can last forever.

Fix this by don't enable irq and use safe_halt() as suggested by Sean
Christopherson.

Signed-off-by: Peter Xu <peterx@redhat.com>
---
 x86/tscdeadline_latency.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

Patch
diff mbox series

diff --git a/x86/tscdeadline_latency.c b/x86/tscdeadline_latency.c
index 0617a1b..3ad2950 100644
--- a/x86/tscdeadline_latency.c
+++ b/x86/tscdeadline_latency.c
@@ -70,8 +70,6 @@  static void tsc_deadline_timer_isr(isr_regs_t *regs)
 static void start_tsc_deadline_timer(void)
 {
     handle_irq(TSC_DEADLINE_TIMER_VECTOR, tsc_deadline_timer_isr);
-    irq_enable();
-
     wrmsr(MSR_IA32_TSCDEADLINE, rdmsr(MSR_IA32_TSC)+delta);
     asm volatile ("nop");
 }
@@ -116,10 +114,9 @@  int main(int argc, char **argv)
     breakmax = argc <= 3 ? 0 : atol(argv[3]);
     printf("breakmax=%d\n", breakmax);
     test_tsc_deadline_timer();
-    irq_enable();
 
     do {
-        asm volatile("hlt");
+        safe_halt();
     } while (!hitmax && table_idx < size);
 
     for (i = 0; i < table_idx; i++) {