PCI: dwc: avoid OOB read in find_next_bit
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Message ID 20190712132611.3374-1-l.stach@pengutronix.de
State New
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Series
  • PCI: dwc: avoid OOB read in find_next_bit
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Commit Message

Lucas Stach July 12, 2019, 1:26 p.m. UTC
Find_next_bit works on a long type, which causes a OOB read on the
u32 input when used on ARM64.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/pci/controller/dwc/pcie-designware-host.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

Comments

Ahmad Fatoum July 12, 2019, 1:54 p.m. UTC | #1
Hello Lucas,

On 7/12/19 3:26 PM, Lucas Stach wrote:
> Find_next_bit works on a long type, which causes a OOB read on the
> u32 input when used on ARM64.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  drivers/pci/controller/dwc/pcie-designware-host.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 77db32529319..81a2139d68d6 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -78,15 +78,16 @@ static struct msi_domain_info dw_pcie_msi_domain_info = {
>  irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
>  {
>  	int i, pos, irq;
> -	u32 val, num_ctrls;
> +	u32 num_ctrls;
>  	irqreturn_t ret = IRQ_NONE;
> +	unsigned long val;
>  
>  	num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
>  
>  	for (i = 0; i < num_ctrls; i++) {
>  		dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS +
>  					(i * MSI_REG_CTRL_BLOCK_SIZE),
> -				    4, &val);
> +				    4, (u32 *)&val);

Wouldn't this still be wrong on big-endian 64-bit systems?
You're writing the first 4 bytes here, leaving the higher 4 uninitialized.
find_next_bit will read the lowest-valued 32-bits, i.e. the highest
four on ARM64, which are uninitialized.


>  		if (!val)
>  			continue;
>  
>
Bjorn Helgaas July 12, 2019, 2:07 p.m. UTC | #2
On Fri, Jul 12, 2019 at 03:26:11PM +0200, Lucas Stach wrote:
> Find_next_bit works on a long type, which causes a OOB read on the
> u32 input when used on ARM64.

s/Find_next_bit/find_next_bit()/ so it's obviously a function name and
we can directly grep for it (in subject also, and capitalize "Avoid").

Please spell out "OOB"; I *assume* that means "out of bounds"?

> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  drivers/pci/controller/dwc/pcie-designware-host.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 77db32529319..81a2139d68d6 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -78,15 +78,16 @@ static struct msi_domain_info dw_pcie_msi_domain_info = {
>  irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
>  {
>  	int i, pos, irq;
> -	u32 val, num_ctrls;
> +	u32 num_ctrls;
>  	irqreturn_t ret = IRQ_NONE;
> +	unsigned long val;
>  
>  	num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
>  
>  	for (i = 0; i < num_ctrls; i++) {
>  		dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS +
>  					(i * MSI_REG_CTRL_BLOCK_SIZE),
> -				    4, &val);
> +				    4, (u32 *)&val);

I agree that the "val" we pass to find_next_bit() needs to be an
"unsigned long", so I like that part.

It's not completely obvious to me that it's safe to cast "val" to
"u32 *" here; does that do the right thing regardless of byte order?

Doing something like:

  u32 status;
  unsigned long val;

  dw_pcie_rd_own_conf(..., &status);

  val = status;
  find_next_bit(&val, ...);

would be more obvious to me.

>  		if (!val)
>  			continue;
>  
> -- 
> 2.20.1
>

Patch
diff mbox series

diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 77db32529319..81a2139d68d6 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -78,15 +78,16 @@  static struct msi_domain_info dw_pcie_msi_domain_info = {
 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
 {
 	int i, pos, irq;
-	u32 val, num_ctrls;
+	u32 num_ctrls;
 	irqreturn_t ret = IRQ_NONE;
+	unsigned long val;
 
 	num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
 
 	for (i = 0; i < num_ctrls; i++) {
 		dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS +
 					(i * MSI_REG_CTRL_BLOCK_SIZE),
-				    4, &val);
+				    4, (u32 *)&val);
 		if (!val)
 			continue;