| Message ID | 2fa725fbc09306f1a95befc62715a708b4c0fad0.1562940244.git.saiprakash.ranjan@codeaurora.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add coresight support for SDM845, MSM8998 and MSM8996 | expand |
On Fri, Jul 12, 2019 at 07:46:25PM +0530, Sai Prakash Ranjan wrote: > From: Vivek Gautam <vivek.gautam@codeaurora.org> > > Enable coresight support by adding device nodes for the > available source, sinks and channel blocks on msm8996. > > This also adds coresight cpu debug nodes. > > Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> > Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> > Acked-By: Suzuki K Poulose <suzuki.poulose@arm.com> > --- > arch/arm64/boot/dts/qcom/msm8996.dtsi | 434 ++++++++++++++++++++++++++ > 1 file changed, 434 insertions(+) > We've gone trhough 8 iteration of this set and I'm still finding checkpatch problems, and I'm not referring to lines over 80 characters. > diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi > index 96c0a481f454..8968431e772c 100644 > --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi > +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi > @@ -633,6 +633,440 @@ > reg = <0x300000 0x90000>; > }; > > + stm@3002000 { > + compatible = "arm,coresight-stm", "arm,primecell"; > + reg = <0x3002000 0x1000>, > + <0x8280000 0x180000>; > + reg-names = "stm-base", "stm-stimulus-base"; > + > + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; > + clock-names = "apb_pclk", "atclk"; > + > + out-ports { > + port { > + stm_out: endpoint { > + remote-endpoint = > + <&funnel0_in>; > + }; > + }; > + }; > + }; > + > + tpiu@3020000 { > + compatible = "arm,coresight-tpiu", "arm,primecell"; > + reg = <0x3020000 0x1000>; > + > + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; > + clock-names = "apb_pclk", "atclk"; > + > + in-ports { > + port { > + tpiu_in: endpoint { > + remote-endpoint = > + <&replicator_out1>; > + }; > + }; > + }; > + }; > + > + funnel@3021000 { > + compatible = "arm,coresight-funnel", "arm,primecell"; > + reg = <0x3021000 0x1000>; > + > + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; > + clock-names = "apb_pclk", "atclk"; > + > + in-ports { > + port { > + funnel0_in: endpoint { > + remote-endpoint = > + <&stm_out>; > + }; > + }; > + }; > + > + out-ports { > + port { > + funnel0_out: endpoint { > + remote-endpoint = > + <&merge_funnel_in0>; > + }; > + }; > + }; > + }; > + > + funnel@3022000 { > + compatible = "arm,coresight-funnel", "arm,primecell"; > + reg = <0x3022000 0x1000>; > + > + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; > + clock-names = "apb_pclk", "atclk"; > + > + in-ports { > + port { > + funnel1_in: endpoint { > + remote-endpoint = > + <&apss_merge_funnel_out>; > + }; > + }; > + }; > + > + out-ports { > + port { > + funnel1_out: endpoint { > + remote-endpoint = > + <&merge_funnel_in1>; > + }; > + }; > + }; > + }; > + > + funnel@3025000 { > + compatible = "arm,coresight-funnel", "arm,primecell"; > + reg = <0x3025000 0x1000>; > + > + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; > + clock-names = "apb_pclk", "atclk"; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + merge_funnel_in0: endpoint { > + remote-endpoint = > + <&funnel0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + merge_funnel_in1: endpoint { > + remote-endpoint = > + <&funnel1_out>; > + }; > + }; > + }; > + > + out-ports { > + port { > + merge_funnel_out: endpoint { > + remote-endpoint = > + <&etf_in>; > + }; > + }; > + }; > + }; > + > + replicator@3026000 { > + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; > + reg = <0x3026000 0x1000>; > + > + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; > + clock-names = "apb_pclk", "atclk"; > + > + in-ports { > + port { > + replicator_in: endpoint { > + remote-endpoint = > + <&etf_out>; > + }; > + }; > + }; > + > + out-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + replicator_out0: endpoint { > + remote-endpoint = > + <&etr_in>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + replicator_out1: endpoint { > + remote-endpoint = > + <&tpiu_in>; > + }; > + }; > + }; > + }; > + > + etf@3027000 { > + compatible = "arm,coresight-tmc", "arm,primecell"; > + reg = <0x3027000 0x1000>; > + > + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; > + clock-names = "apb_pclk", "atclk"; > + > + in-ports { > + port { > + etf_in: endpoint { > + remote-endpoint = > + <&merge_funnel_out>; > + }; > + }; > + }; > + > + out-ports { > + port { > + etf_out: endpoint { > + remote-endpoint = > + <&replicator_in>; > + }; > + }; > + }; > + }; > + > + etr@3028000 { > + compatible = "arm,coresight-tmc", "arm,primecell"; > + reg = <0x3028000 0x1000>; > + > + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; > + clock-names = "apb_pclk", "atclk"; > + arm,scatter-gather; > + > + in-ports { > + port { > + etr_in: endpoint { > + remote-endpoint = > + <&replicator_out0>; > + }; > + }; > + }; > + }; > + > + debug@3810000 { > + compatible = "arm,coresight-cpu-debug", "arm,primecell"; > + reg = <0x3810000 0x1000>; > + > + clocks = <&rpmcc RPM_QDSS_CLK>; > + clock-names = "apb_pclk"; > + > + cpu = <&CPU0>; > + }; > + > + etm@3840000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0x3840000 0x1000>; > + > + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; > + clock-names = "apb_pclk", "atclk"; > + > + cpu = <&CPU0>; > + > + out-ports { > + port { > + etm0_out: endpoint { > + remote-endpoint = > + <&apss_funnel0_in0>; > + }; > + }; > + }; > + }; > + > + debug@3910000 { > + compatible = "arm,coresight-cpu-debug", "arm,primecell"; > + reg = <0x3910000 0x1000>; > + > + clocks = <&rpmcc RPM_QDSS_CLK>; > + clock-names = "apb_pclk"; > + > + cpu = <&CPU1>; > + }; > + > + etm@3940000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0x3940000 0x1000>; > + > + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; > + clock-names = "apb_pclk", "atclk"; > + > + cpu = <&CPU1>; > + > + out-ports { > + port { > + etm1_out: endpoint { > + remote-endpoint = > + <&apss_funnel0_in1>; > + }; > + }; > + }; > + }; > + > + funnel@39b0000 { /* APSS Funnel 0 */ > + compatible = "arm,coresight-funnel", "arm,primecell"; > + reg = <0x39b0000 0x1000>; > + > + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; > + clock-names = "apb_pclk", "atclk"; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + apss_funnel0_in0: endpoint { > + remote-endpoint = <&etm0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + apss_funnel0_in1: endpoint { > + remote-endpoint = <&etm1_out>; > + }; > + }; > + }; > + > + out-ports { > + port { > + apss_funnel0_out: endpoint { > + remote-endpoint = > + <&apss_merge_funnel_in0>; > + }; > + }; > + }; > + }; > + > + debug@3a10000 { > + compatible = "arm,coresight-cpu-debug", "arm,primecell"; > + reg = <0x3a10000 0x1000>; > + > + clocks = <&rpmcc RPM_QDSS_CLK>; > + clock-names = "apb_pclk"; > + > + cpu = <&CPU2>; > + }; > + > + etm@3a40000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0x3a40000 0x1000>; > + > + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; > + clock-names = "apb_pclk", "atclk"; > + > + cpu = <&CPU2>; > + > + out-ports { > + port { > + etm2_out: endpoint { > + remote-endpoint = > + <&apss_funnel1_in0>; > + }; > + }; > + }; > + }; > + > + debug@3b10000 { > + compatible = "arm,coresight-cpu-debug", "arm,primecell"; > + reg = <0x3b10000 0x1000>; > + > + clocks = <&rpmcc RPM_QDSS_CLK>; > + clock-names = "apb_pclk"; > + > + cpu = <&CPU3>; > + }; > + > + etm@3b40000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0x3b40000 0x1000>; > + > + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; > + clock-names = "apb_pclk", "atclk"; > + > + cpu = <&CPU3>; > + > + out-ports { > + port { > + etm3_out: endpoint { > + remote-endpoint = > + <&apss_funnel1_in1>; > + }; > + }; > + }; > + }; > + > + funnel@3bb0000 { /* APSS Funnel 1 */ > + compatible = "arm,coresight-funnel", "arm,primecell"; > + reg = <0x3bb0000 0x1000>; > + > + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; > + clock-names = "apb_pclk", "atclk"; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + apss_funnel1_in0: endpoint { > + remote-endpoint = <&etm2_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + apss_funnel1_in1: endpoint { > + remote-endpoint = <&etm3_out>; > + }; > + }; > + }; > + > + out-ports { > + port { > + apss_funnel1_out: endpoint { > + remote-endpoint = > + <&apss_merge_funnel_in1>; > + }; > + }; > + }; > + }; > + > + funnel@3bc0000 { > + compatible = "arm,coresight-funnel", "arm,primecell"; > + reg = <0x3bc0000 0x1000>; > + > + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; > + clock-names = "apb_pclk", "atclk"; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + apss_merge_funnel_in0: endpoint { > + remote-endpoint = > + <&apss_funnel0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + apss_merge_funnel_in1: endpoint { > + remote-endpoint = > + <&apss_funnel1_out>; > + }; > + }; > + }; > + > + out-ports { > + port { > + apss_merge_funnel_out: endpoint { > + remote-endpoint = > + <&funnel1_in>; > + }; > + }; > + }; > + }; > + > kryocc: clock-controller@6400000 { > compatible = "qcom,apcc-msm8996"; > reg = <0x6400000 0x90000>; > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation >
Hi Mathieu, On 7/17/2019 10:30 PM, Mathieu Poirier wrote: > On Fri, Jul 12, 2019 at 07:46:25PM +0530, Sai Prakash Ranjan wrote: >> From: Vivek Gautam <vivek.gautam@codeaurora.org> >> >> Enable coresight support by adding device nodes for the >> available source, sinks and channel blocks on msm8996. >> >> This also adds coresight cpu debug nodes. >> >> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> >> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> >> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> >> Acked-By: Suzuki K Poulose <suzuki.poulose@arm.com> >> --- >> arch/arm64/boot/dts/qcom/msm8996.dtsi | 434 ++++++++++++++++++++++++++ >> 1 file changed, 434 insertions(+) >> > > We've gone trhough 8 iteration of this set and I'm still finding checkpatch > problems, and I'm not referring to lines over 80 characters. > I only get below 2 checkpatch warnings: If you are talking about the below one, then it was not added manually. It was taken automatically when I pulled in the v7. Should I be resending this patch for this? $ ./scripts/checkpatch.pl -g 2fa725fbc09306f1a95befc62715a708b4c0fad0 WARNING: 'Acked-by:' is the preferred signature form #14: Acked-By: Suzuki K Poulose <suzuki.poulose@arm.com> WARNING: line over 80 characters #154: FILE: arch/arm64/boot/dts/qcom/msm8996.dtsi:763: + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; total: 0 errors, 2 warnings, 440 lines checked -Sai
On Wed, 17 Jul 2019 at 23:47, Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> wrote: > > Hi Mathieu, > > On 7/17/2019 10:30 PM, Mathieu Poirier wrote: > > On Fri, Jul 12, 2019 at 07:46:25PM +0530, Sai Prakash Ranjan wrote: > >> From: Vivek Gautam <vivek.gautam@codeaurora.org> > >> > >> Enable coresight support by adding device nodes for the > >> available source, sinks and channel blocks on msm8996. > >> > >> This also adds coresight cpu debug nodes. > >> > >> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> > >> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > >> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> > >> Acked-By: Suzuki K Poulose <suzuki.poulose@arm.com> > >> --- > >> arch/arm64/boot/dts/qcom/msm8996.dtsi | 434 ++++++++++++++++++++++++++ > >> 1 file changed, 434 insertions(+) > >> > > > > We've gone trhough 8 iteration of this set and I'm still finding checkpatch > > problems, and I'm not referring to lines over 80 characters. > > > > I only get below 2 checkpatch warnings: > > If you are talking about the below one, then it was not added manually. > It was taken automatically when I pulled in the v7. Should I be > resending this patch for this? That depends if you want David and Andy to pickup your patches - I am sure they'll point out exactly the same thing. > > $ ./scripts/checkpatch.pl -g 2fa725fbc09306f1a95befc62715a708b4c0fad0 > WARNING: 'Acked-by:' is the preferred signature form > #14: > Acked-By: Suzuki K Poulose <suzuki.poulose@arm.com> > > WARNING: line over 80 characters > #154: FILE: arch/arm64/boot/dts/qcom/msm8996.dtsi:763: > + compatible = "arm,coresight-dynamic-replicator", > "arm,primecell"; > > total: 0 errors, 2 warnings, 440 lines checked > > > -Sai > > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation
On Thu 18 Jul 08:31 PDT 2019, Mathieu Poirier wrote: > On Wed, 17 Jul 2019 at 23:47, Sai Prakash Ranjan > <saiprakash.ranjan@codeaurora.org> wrote: > > > > Hi Mathieu, > > > > On 7/17/2019 10:30 PM, Mathieu Poirier wrote: > > > On Fri, Jul 12, 2019 at 07:46:25PM +0530, Sai Prakash Ranjan wrote: > > >> From: Vivek Gautam <vivek.gautam@codeaurora.org> > > >> > > >> Enable coresight support by adding device nodes for the > > >> available source, sinks and channel blocks on msm8996. > > >> > > >> This also adds coresight cpu debug nodes. > > >> > > >> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org> > > >> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > > >> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> > > >> Acked-By: Suzuki K Poulose <suzuki.poulose@arm.com> > > >> --- > > >> arch/arm64/boot/dts/qcom/msm8996.dtsi | 434 ++++++++++++++++++++++++++ > > >> 1 file changed, 434 insertions(+) > > >> > > > > > > We've gone trhough 8 iteration of this set and I'm still finding checkpatch > > > problems, and I'm not referring to lines over 80 characters. > > > > > > > I only get below 2 checkpatch warnings: > > > > If you are talking about the below one, then it was not added manually. > > It was taken automatically when I pulled in the v7. Should I be > > resending this patch for this? > > That depends if you want David and Andy to pickup your patches - I am > sure they'll point out exactly the same thing. > If it's only the capitalization of "By" then I'll just fix it up as I apply the patches (thanks for pointing it out though!). But it seems the discussion on patch 2 needs to settle(?) (And the merge window has to close). Regards, Bjorn > > > > $ ./scripts/checkpatch.pl -g 2fa725fbc09306f1a95befc62715a708b4c0fad0 > > WARNING: 'Acked-by:' is the preferred signature form > > #14: > > Acked-By: Suzuki K Poulose <suzuki.poulose@arm.com> > > > > WARNING: line over 80 characters > > #154: FILE: arch/arm64/boot/dts/qcom/msm8996.dtsi:763: > > + compatible = "arm,coresight-dynamic-replicator", > > "arm,primecell"; > > > > total: 0 errors, 2 warnings, 440 lines checked > > > > > > -Sai > > > > -- > > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > > of Code Aurora Forum, hosted by The Linux Foundation
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 96c0a481f454..8968431e772c 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -633,6 +633,440 @@ reg = <0x300000 0x90000>; }; + stm@3002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x3002000 0x1000>, + <0x8280000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = + <&funnel0_in>; + }; + }; + }; + }; + + tpiu@3020000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0x3020000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + port { + tpiu_in: endpoint { + remote-endpoint = + <&replicator_out1>; + }; + }; + }; + }; + + funnel@3021000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x3021000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + port { + funnel0_in: endpoint { + remote-endpoint = + <&stm_out>; + }; + }; + }; + + out-ports { + port { + funnel0_out: endpoint { + remote-endpoint = + <&merge_funnel_in0>; + }; + }; + }; + }; + + funnel@3022000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x3022000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + port { + funnel1_in: endpoint { + remote-endpoint = + <&apss_merge_funnel_out>; + }; + }; + }; + + out-ports { + port { + funnel1_out: endpoint { + remote-endpoint = + <&merge_funnel_in1>; + }; + }; + }; + }; + + funnel@3025000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x3025000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + merge_funnel_in0: endpoint { + remote-endpoint = + <&funnel0_out>; + }; + }; + + port@1 { + reg = <1>; + merge_funnel_in1: endpoint { + remote-endpoint = + <&funnel1_out>; + }; + }; + }; + + out-ports { + port { + merge_funnel_out: endpoint { + remote-endpoint = + <&etf_in>; + }; + }; + }; + }; + + replicator@3026000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x3026000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint = + <&etf_out>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator_out0: endpoint { + remote-endpoint = + <&etr_in>; + }; + }; + + port@1 { + reg = <1>; + replicator_out1: endpoint { + remote-endpoint = + <&tpiu_in>; + }; + }; + }; + }; + + etf@3027000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x3027000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + port { + etf_in: endpoint { + remote-endpoint = + <&merge_funnel_out>; + }; + }; + }; + + out-ports { + port { + etf_out: endpoint { + remote-endpoint = + <&replicator_in>; + }; + }; + }; + }; + + etr@3028000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x3028000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + arm,scatter-gather; + + in-ports { + port { + etr_in: endpoint { + remote-endpoint = + <&replicator_out0>; + }; + }; + }; + }; + + debug@3810000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x3810000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU0>; + }; + + etm@3840000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x3840000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU0>; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = + <&apss_funnel0_in0>; + }; + }; + }; + }; + + debug@3910000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x3910000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU1>; + }; + + etm@3940000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x3940000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU1>; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = + <&apss_funnel0_in1>; + }; + }; + }; + }; + + funnel@39b0000 { /* APSS Funnel 0 */ + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x39b0000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel0_in0: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_funnel0_in1: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + }; + + out-ports { + port { + apss_funnel0_out: endpoint { + remote-endpoint = + <&apss_merge_funnel_in0>; + }; + }; + }; + }; + + debug@3a10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x3a10000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU2>; + }; + + etm@3a40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x3a40000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU2>; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = + <&apss_funnel1_in0>; + }; + }; + }; + }; + + debug@3b10000 { + compatible = "arm,coresight-cpu-debug", "arm,primecell"; + reg = <0x3b10000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>; + clock-names = "apb_pclk"; + + cpu = <&CPU3>; + }; + + etm@3b40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x3b40000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + cpu = <&CPU3>; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = + <&apss_funnel1_in1>; + }; + }; + }; + }; + + funnel@3bb0000 { /* APSS Funnel 1 */ + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x3bb0000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_funnel1_in0: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + + port@1 { + reg = <1>; + apss_funnel1_in1: endpoint { + remote-endpoint = <&etm3_out>; + }; + }; + }; + + out-ports { + port { + apss_funnel1_out: endpoint { + remote-endpoint = + <&apss_merge_funnel_in1>; + }; + }; + }; + }; + + funnel@3bc0000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x3bc0000 0x1000>; + + clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; + clock-names = "apb_pclk", "atclk"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + apss_merge_funnel_in0: endpoint { + remote-endpoint = + <&apss_funnel0_out>; + }; + }; + + port@1 { + reg = <1>; + apss_merge_funnel_in1: endpoint { + remote-endpoint = + <&apss_funnel1_out>; + }; + }; + }; + + out-ports { + port { + apss_merge_funnel_out: endpoint { + remote-endpoint = + <&funnel1_in>; + }; + }; + }; + }; + kryocc: clock-controller@6400000 { compatible = "qcom,apcc-msm8996"; reg = <0x6400000 0x90000>;