diff mbox series

[v1,12/50] clk: add ID to PWM MUX in Exynos5420

Message ID	20190715124417.4787-13-l.luba@partner.samsung.com (mailing list archive)
State	Not Applicable
Headers	show Return-Path: <linux-samsung-soc-owner@kernel.org> From: Lukasz Luba <l.luba@partner.samsung.com> To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: mturquette@baylibre.com, sboyd@kernel.org, b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, mark.rutland@arm.com, robh+dt@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, a.hajda@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, Lukasz Luba <l.luba@partner.samsung.com> Subject: [PATCH v1 12/50] clk: add ID to PWM MUX in Exynos5420 Date: Mon, 15 Jul 2019 14:43:39 +0200 Message-Id: <20190715124417.4787-13-l.luba@partner.samsung.com> In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com> Content-Type: text/plain; charset="utf-8" CMS-TYPE: 201P References: <20190715124417.4787-1-l.luba@partner.samsung.com> <CGME20190715124443eucas1p1adf02a02bf77448f2277ddd5fe5e895b@eucas1p1.samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk
Series	[v1,01/50] clk: samsung: add new IDs for Exynos5420 clocks \| expand [v1,01/50] clk: samsung: add new IDs for Exynos5420 clocks [v1,02/50] clk: samsung: add IDs for Exynos5420 NoC clocks [v1,03/50] clk: samsung: change parent of dout_aclk400_wcore in Exynos5420 [v1,04/50] clk: samsung: add IDs to manage aclk400_mscl in Exynos5420 [v1,05/50] clk: samsung: add IDs to aclk400_isp in Exynos5420 [v1,06/50] clk: samsung: add IDs to ACLK266 clocks in Exynos5420 [v1,07/50] clk: samsung: add IDs to ACLK266_G2D clocks in Exynos5420 [v1,08/50] clk: samsung: change aclk266_isp clocks definitions Exynos5420 [v1,09/50] clk: samsung: add IDs to FSYS clocks in Exynos5x [v1,10/50] clk: samsung: change ACLK100_NOC clocks definitions Exynos5x [v1,11/50] clk: samsung: add IDs to UART clocks in Exynos5420 [v1,12/50] clk: add ID to PWM MUX in Exynos5420 [v1,13/50] clk: samsung: add DPLL rate table in Exynos5420 [v1,14/50] clk: samsung: add CLK_MOUT_SCLK_CPLL in the Exynos5420 [v1,15/50] clk: samsung: add MPLL rate table in Exynos5420 [v1,16/50] clk: samsung: add SPLL rate table in Exynos5420 [v1,17/50] clk: samsung: add CLK_MOUT_MMC0 in the Exynos5420 [v1,18/50] ARM: dts: exynos: add bus_isp with OPP table [v1,19/50] ARM: dts: exynos: change OPPs values for FSYS2 in Exynos5420 [v1,20/50] ARM: dts: exynos: change and rename FSYS OPP table in Exynos5420 [v1,21/50] ARM: dts: exynos: add OPP into FSYS APB bus in Exynos5420 [v1,22/50] ARM: dts: exynos: OPPs for bus_disp1 in Exynos5420 [v1,23/50] ARM: dts: exynos: change lowest OPP in bus_disp1_fimd in Exynos5420 [v1,24/50] ARM: dts: exynos: align OPPs with PLL rate for MSCL in Exynos5420 [v1,25/50] ARM: dts: exynos: add 300MHz to bus_disp1_fimd in Exynos5420 [v1,26/50] ARM: dts: exynos: align NOC100 bus OPPs in Exynos5420 [v1,27/50] ARM: dts: exynos: align bus_wcore OPPs in Exynos5420 [v1,28/50] ARM: dts: exynos: change OPPs for g2d and g2d_acp buses in Exynos5420 [v1,29/50] ARM: dts: exynos: align OPPs of bus_gen in Exynos5420 [v1,30/50] ARM: dts: exynos: add bus_isp266 into Exynos5800 [v1,31/50] ARM: dts: exynos: align lowest OPP in bus_jpeg in Exynos5420 [v1,32/50] ARM: dts: exynos: remove lowest OPP from bus_mfc in Exynos5420 [v1,33/50] ARM: dts: exynos: set parent clocks to UARTs in Exynos5420 [v1,34/50] ARM: dts: exynos: set parent clocks to PWM in Exynos5420 [v1,35/50] ARM: dts: exynos: change speed and parent of NoC clock in Exynos5420 [v1,36/50] ARM: dts: exynos: change ACLK100_NOC config in Exynos5422 [v1,37/50] ARM: dts: exynos: change parent and rate of bus_fsys in Exynos5422 [v1,38/50] ARM: dts: exynos: change parent and rate of bus_fsys2 in Exynos5422 [v1,39/50] ARM: dts: exynos: change parent and rate of bus_fsys_acp in Exynos5422 [v1,40/50] ARM: dts: exynos: change parent and rate of bus_gen in Exynos5422 [v1,41/50] ARM: dts: exynos: change parent and rate of bus_g2d in Exynos5422 [v1,42/50] ARM: dts: exynos: change parent and rate of bus_mscl in Exynos5422 [v1,43/50] ARM: dts: exynos: add bus_isp in Exynos5422 [v1,44/50] ARM: dts: exynos: change rate of bus_jpeg in Exynos5422 [v1,45/50] ARM: dts: exynos: change rate of bus_disp1_fimd in Exynos5422 [v1,46/50] ARM: dts: exynos: change rates of bus_disp1 in Exynos5422 [v1,47/50] ARM: dts: exynos: change rate of bus_gscl_scaler in Exynos5422 [v1,48/50] ARM: dts: exynos: set proper parents to bus_isp266 Exynos5422 [v1,49/50] ARM: dts: exynos: add buses support for Exynos5800 Peach Pi [v1,50/50] ARM: dts: exynos: change MMC0 clock parent in Exynos5800 Peach Pi

Commit Message

Lukasz Luba July 15, 2019, 12:43 p.m. UTC

Add ID to PWM MUX to manage it from DT to reflect proper topology.

Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff mbox series

Patch

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 7bf74401c4e7..7f8221527633 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -772,7 +772,7 @@  static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
 	MUX(CLK_MOUT_UART1, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
 	MUX(CLK_MOUT_UART2, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
 	MUX(CLK_MOUT_UART3, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
-	MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
+	MUX(CLK_MOUT_PWM, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
 	MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
 	MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
 	MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3),