diff mbox series

[4.19.y-cip,01/23] clk: renesas: r8a774a1: Add CPEX clock

Message ID	1563197408-59548-2-git-send-email-biju.das@bp.renesas.com (mailing list archive)
State	Accepted
Headers	show Return-Path: <cip-dev-bounces@lists.cip-project.org> From: Biju Das <biju.das@bp.renesas.com> To: cip-dev@lists.cip-project.org Date: Mon, 15 Jul 2019 14:29:46 +0100 Message-Id: <1563197408-59548-2-git-send-email-biju.das@bp.renesas.com> In-Reply-To: <1563197408-59548-1-git-send-email-biju.das@bp.renesas.com> References: <1563197408-59548-1-git-send-email-biju.das@bp.renesas.com> Cc: Biju Das <biju.das@bp.renesas.com> Subject: [cip-dev] [PATCH 4.19.y-cip 01/23] clk: renesas: r8a774a1: Add CPEX clock Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: cip-dev-bounces@lists.cip-project.org Errors-To: cip-dev-bounces@lists.cip-project.org
Series	Clock enhancements \| expand [4.19.y-cip,00/23] Clock enhancements [4.19.y-cip,01/23] clk: renesas: r8a774a1: Add CPEX clock [4.19.y-cip,02/23] clk: renesas: rcar-gen3: Set state when registering SD clocks [4.19.y-cip,03/23] clk: renesas: rcar-gen3: Add documentation for SD clocks [4.19.y-cip,04/23] clk: renesas: rcar-gen3: Add HS400 quirk for SD clock [4.19.y-cip,05/23] clk: renesas: Remove usage of CLK_IS_BASIC [4.19.y-cip,06/23] clk: renesas: r8a774a1: Add missing CANFD clock [4.19.y-cip,07/23] clk: renesas: rcar-gen3: Factor out cpg_reg_modify() [4.19.y-cip,08/23] clk: renesas: rcar-gen3: Add spinlock [4.19.y-cip,09/23] clk: renesas: r8a774a1: Fix LAST_DT_CORE_CLK [4.19.y-cip,10/23] clk: renesas: rcar-gen3: Pass name/offset to cpg_sd_clk_register() [4.19.y-cip,11/23] clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor [4.19.y-cip,12/23] clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset [4.19.y-cip,13/23] clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2 [4.19.y-cip,14/23] math64: New DIV64_U64_ROUND_CLOSEST helper [4.19.y-cip,15/23] clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parents [4.19.y-cip,16/23] clk: renesas: r8a774c0: Add Z2 clock [4.19.y-cip,17/23] clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI [4.19.y-cip,18/23] clk: renesas: rcar-gen3: Correct parent clock of HS-USB [4.19.y-cip,19/23] clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC [4.19.y-cip,20/23] clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC [4.19.y-cip,21/23] clk: renesas: rcar-gen3: Fix cpg_sd_clock_round_rate() return value [4.19.y-cip,22/23] clk: renesas: rcar-gen3: Remove unused variable [4.19.y-cip,23/23] arm64: dts: renesas: r8a774c0: Add OPPs table for cpu devices

Commit Message

Biju Das July 15, 2019, 1:29 p.m. UTC

From: Geert Uytterhoeven <geert+renesas@glider.be>

commit f845b01d478a4d139fe3493f1e6ec8d9110ce56c upstream.

Implement support for the CPEX clock on RZ/G2M.  This clock can be
selected as a clock source for CMT1 (Compare Match Timer Type 1).

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
---
 drivers/clk/renesas/r8a774a1-cpg-mssr.c | 1 +
 1 file changed, 1 insertion(+)

diff mbox series

Patch

diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
index b0da342..10e8525 100644
--- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -100,6 +100,7 @@  static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
 
 	DEF_FIXED("cl",         R8A774A1_CLK_CL,    CLK_PLL1_DIV2, 48, 1),
 	DEF_FIXED("cp",         R8A774A1_CLK_CP,    CLK_EXTAL,      2, 1),
+	DEF_FIXED("cpex",       R8A774A1_CLK_CPEX,  CLK_EXTAL,      2, 1),
 
 	DEF_DIV6P1("csi0",      R8A774A1_CLK_CSI0,  CLK_PLL1_DIV4, 0x00c),
 	DEF_DIV6P1("mso",       R8A774A1_CLK_MSO,   CLK_PLL1_DIV4, 0x014),