[v3,29/57] ram: rk3399: Configure PHY RX_CM_INPUT for lpddr4
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Message ID 20190716115745.12585-30-jagan@amarulasolutions.com
State New
Headers show
Series
  • ram: rk3399: Add LPDDR4 support
Related show

Commit Message

Jagan Teki July 16, 2019, 11:57 a.m. UTC
Configure PHY RX_CM_INPUT for lpddr4 during phy IO config.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
 drivers/ram/rockchip/sdram_rk3399.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

Comments

Kever Yang July 16, 2019, 1:13 p.m. UTC | #1
On 2019/7/16 下午7:57, Jagan Teki wrote:
> Configure PHY RX_CM_INPUT for lpddr4 during phy IO config.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> Signed-off-by: YouMin Chen <cym@rock-chips.com>

Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>

Thanks,
  - Kever
> ---
>   drivers/ram/rockchip/sdram_rk3399.c | 22 ++++++++++++++++++++++
>   1 file changed, 22 insertions(+)
>
> diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
> index c02f936f2a..2ab10da53f 100644
> --- a/drivers/ram/rockchip/sdram_rk3399.c
> +++ b/drivers/ram/rockchip/sdram_rk3399.c
> @@ -39,6 +39,7 @@
>   #define PHY_BOOSTN_EN		0x1
>   #define PHY_SLEWP_EN		0x1
>   #define PHY_SLEWN_EN		0x1
> +#define PHY_RX_CM_INPUT		0x1
>   
>   #define CRU_SFTRST_DDR_CTRL(ch, n)	((0x1 << (8 + 16 + (ch) * 4)) | \
>   					((n) << (8 + (ch) * 4)))
> @@ -384,6 +385,27 @@ static int phy_io_config(const struct chan_info *chan,
>   	/* PHY_939 PHY_PAD_CS_DRIVE */
>   	clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
>   
> +	if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
> +		/* RX_CM_INPUT */
> +		reg_value = PHY_RX_CM_INPUT;
> +		/* PHY_924 PHY_PAD_FDBK_DRIVE */
> +		clrsetbits_le32(&denali_phy[924], 0x1 << 14, reg_value << 14);
> +		/* PHY_926 PHY_PAD_DATA_DRIVE */
> +		clrsetbits_le32(&denali_phy[926], 0x1 << 11, reg_value << 11);
> +		/* PHY_927 PHY_PAD_DQS_DRIVE */
> +		clrsetbits_le32(&denali_phy[927], 0x1 << 13, reg_value << 13);
> +		/* PHY_928 PHY_PAD_ADDR_DRIVE */
> +		clrsetbits_le32(&denali_phy[928], 0x1 << 19, reg_value << 19);
> +		/* PHY_929 PHY_PAD_CLK_DRIVE */
> +		clrsetbits_le32(&denali_phy[929], 0x1 << 21, reg_value << 21);
> +		/* PHY_935 PHY_PAD_CKE_DRIVE */
> +		clrsetbits_le32(&denali_phy[935], 0x1 << 19, reg_value << 19);
> +		/* PHY_937 PHY_PAD_RST_DRIVE */
> +		clrsetbits_le32(&denali_phy[937], 0x1 << 19, reg_value << 19);
> +		/* PHY_939 PHY_PAD_CS_DRIVE */
> +		clrsetbits_le32(&denali_phy[939], 0x1 << 19, reg_value << 19);
> +	}
> +
>   	return 0;
>   }
>

Patch
diff mbox series

diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index c02f936f2a..2ab10da53f 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -39,6 +39,7 @@ 
 #define PHY_BOOSTN_EN		0x1
 #define PHY_SLEWP_EN		0x1
 #define PHY_SLEWN_EN		0x1
+#define PHY_RX_CM_INPUT		0x1
 
 #define CRU_SFTRST_DDR_CTRL(ch, n)	((0x1 << (8 + 16 + (ch) * 4)) | \
 					((n) << (8 + (ch) * 4)))
@@ -384,6 +385,27 @@  static int phy_io_config(const struct chan_info *chan,
 	/* PHY_939 PHY_PAD_CS_DRIVE */
 	clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
 
+	if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
+		/* RX_CM_INPUT */
+		reg_value = PHY_RX_CM_INPUT;
+		/* PHY_924 PHY_PAD_FDBK_DRIVE */
+		clrsetbits_le32(&denali_phy[924], 0x1 << 14, reg_value << 14);
+		/* PHY_926 PHY_PAD_DATA_DRIVE */
+		clrsetbits_le32(&denali_phy[926], 0x1 << 11, reg_value << 11);
+		/* PHY_927 PHY_PAD_DQS_DRIVE */
+		clrsetbits_le32(&denali_phy[927], 0x1 << 13, reg_value << 13);
+		/* PHY_928 PHY_PAD_ADDR_DRIVE */
+		clrsetbits_le32(&denali_phy[928], 0x1 << 19, reg_value << 19);
+		/* PHY_929 PHY_PAD_CLK_DRIVE */
+		clrsetbits_le32(&denali_phy[929], 0x1 << 21, reg_value << 21);
+		/* PHY_935 PHY_PAD_CKE_DRIVE */
+		clrsetbits_le32(&denali_phy[935], 0x1 << 19, reg_value << 19);
+		/* PHY_937 PHY_PAD_RST_DRIVE */
+		clrsetbits_le32(&denali_phy[937], 0x1 << 19, reg_value << 19);
+		/* PHY_939 PHY_PAD_CS_DRIVE */
+		clrsetbits_le32(&denali_phy[939], 0x1 << 19, reg_value << 19);
+	}
+
 	return 0;
 }