[v3,31/57] ram: rk3399: Configure tsel write ca for lpddr4
diff mbox series

Message ID 20190716115745.12585-32-jagan@amarulasolutions.com
State New
Headers show
Series
  • ram: rk3399: Add LPDDR4 support
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Commit Message

Jagan Teki July 16, 2019, 11:57 a.m. UTC
tsel write ca_p and ca_n values need to write on PHY 544, 672
and 800 to configure ds odt.

Configure the same PHY register for lpddr4 would require a mask
value of (300 << 8).

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
 drivers/ram/rockchip/sdram_rk3399.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

Comments

Kever Yang July 16, 2019, 1:14 p.m. UTC | #1
On 2019/7/16 下午7:57, Jagan Teki wrote:
> tsel write ca_p and ca_n values need to write on PHY 544, 672
> and 800 to configure ds odt.
>
> Configure the same PHY register for lpddr4 would require a mask
> value of (300 << 8).
>
> Add support for it.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> Signed-off-by: YouMin Chen <cym@rock-chips.com>

Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>

Thanks,
  - Kever
> ---
>   drivers/ram/rockchip/sdram_rk3399.c | 15 ++++++++++++---
>   1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
> index 7689711a99..1050cbdb07 100644
> --- a/drivers/ram/rockchip/sdram_rk3399.c
> +++ b/drivers/ram/rockchip/sdram_rk3399.c
> @@ -502,9 +502,18 @@ static void set_ds_odt(const struct chan_info *chan,
>   
>   	/* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
>   	reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4);
> -	clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
> -	clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
> -	clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
> +	if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
> +		/* LPDDR4 these register read always return 0, so
> +		 * can not use clrsetbits_le32(), need to write32
> +		 */
> +		writel((0x300 << 8) | reg_value, &denali_phy[544]);
> +		writel((0x300 << 8) | reg_value, &denali_phy[672]);
> +		writel((0x300 << 8) | reg_value, &denali_phy[800]);
> +	} else {
> +		clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
> +		clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
> +		clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
> +	}
>   
>   	/* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */
>   	clrsetbits_le32(&denali_phy[928], 0xff, reg_value);

Patch
diff mbox series

diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 7689711a99..1050cbdb07 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -502,9 +502,18 @@  static void set_ds_odt(const struct chan_info *chan,
 
 	/* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
 	reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4);
-	clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
-	clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
-	clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
+	if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
+		/* LPDDR4 these register read always return 0, so
+		 * can not use clrsetbits_le32(), need to write32
+		 */
+		writel((0x300 << 8) | reg_value, &denali_phy[544]);
+		writel((0x300 << 8) | reg_value, &denali_phy[672]);
+		writel((0x300 << 8) | reg_value, &denali_phy[800]);
+	} else {
+		clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
+		clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
+		clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
+	}
 
 	/* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */
 	clrsetbits_le32(&denali_phy[928], 0xff, reg_value);