[v3,38/57] ram: rk3399: Update lpddr4 vref based on io settings
diff mbox series

Message ID 20190716115745.12585-39-jagan@amarulasolutions.com
State New
Headers show
Series
  • ram: rk3399: Add LPDDR4 support
Related show

Commit Message

Jagan Teki July 16, 2019, 11:57 a.m. UTC
The vref_mode_dq, vref_value_dq on lpddr4 value is depending
on IO settings of rd_vref.

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: YouMin Chen <cym@rock-chips.com>
---
 drivers/ram/rockchip/sdram_rk3399.c | 19 ++++++++++++++-----
 1 file changed, 14 insertions(+), 5 deletions(-)

Comments

Kever Yang July 16, 2019, 1:16 p.m. UTC | #1
On 2019/7/16 下午7:57, Jagan Teki wrote:
> The vref_mode_dq, vref_value_dq on lpddr4 value is depending
> on IO settings of rd_vref.
>
> Add support for it.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> Signed-off-by: YouMin Chen <cym@rock-chips.com>

Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>

Thanks,
  - Kever
> ---
>   drivers/ram/rockchip/sdram_rk3399.c | 19 ++++++++++++++-----
>   1 file changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
> index 9e40880835..4a2622a440 100644
> --- a/drivers/ram/rockchip/sdram_rk3399.c
> +++ b/drivers/ram/rockchip/sdram_rk3399.c
> @@ -338,7 +338,7 @@ static void set_memory_map(const struct chan_info *chan, u32 channel,
>   }
>   
>   static int phy_io_config(const struct chan_info *chan,
> -			 const struct rk3399_sdram_params *params)
> +			 const struct rk3399_sdram_params *params, u32 mr5)
>   {
>   	u32 *denali_phy = chan->publ->denali_phy;
>   	u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
> @@ -349,9 +349,18 @@ static int phy_io_config(const struct chan_info *chan,
>   
>   	/* vref setting */
>   	if (params->base.dramtype == LPDDR4) {
> -		/* LPDDR4 */
> -		vref_mode_dq = 0x6;
> -		vref_value_dq = 0x1f;
> +		struct io_setting *io = lpddr4_get_io_settings(params, mr5);
> +		u32 rd_vref = io->rd_vref * 1000;
> +
> +		if (rd_vref < 36700) {
> +			/* MODE_LV[2:0] = LPDDR4 (Range 2)*/
> +			vref_mode_dq = 0x7;
> +			vref_value_dq = (rd_vref - 3300) / 521;
> +		} else {
> +			/* MODE_LV[2:0] = LPDDR4 (Range 1)*/
> +			vref_mode_dq = 0x6;
> +			vref_value_dq = (rd_vref - 15300) / 521;
> +		}
>   		vref_mode_ac = 0x6;
>   		vref_value_ac = 0x1f;
>   		mode_sel = 0x6;
> @@ -770,7 +779,7 @@ static void set_ds_odt(const struct chan_info *chan,
>   	/* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
>   	clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
>   
> -	phy_io_config(chan, params);
> +	phy_io_config(chan, params, mr5);
>   }
>   
>   static void pctl_start(struct dram_info *dram, u8 channel)

Patch
diff mbox series

diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c
index 9e40880835..4a2622a440 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -338,7 +338,7 @@  static void set_memory_map(const struct chan_info *chan, u32 channel,
 }
 
 static int phy_io_config(const struct chan_info *chan,
-			 const struct rk3399_sdram_params *params)
+			 const struct rk3399_sdram_params *params, u32 mr5)
 {
 	u32 *denali_phy = chan->publ->denali_phy;
 	u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
@@ -349,9 +349,18 @@  static int phy_io_config(const struct chan_info *chan,
 
 	/* vref setting */
 	if (params->base.dramtype == LPDDR4) {
-		/* LPDDR4 */
-		vref_mode_dq = 0x6;
-		vref_value_dq = 0x1f;
+		struct io_setting *io = lpddr4_get_io_settings(params, mr5);
+		u32 rd_vref = io->rd_vref * 1000;
+
+		if (rd_vref < 36700) {
+			/* MODE_LV[2:0] = LPDDR4 (Range 2)*/
+			vref_mode_dq = 0x7;
+			vref_value_dq = (rd_vref - 3300) / 521;
+		} else {
+			/* MODE_LV[2:0] = LPDDR4 (Range 1)*/
+			vref_mode_dq = 0x6;
+			vref_value_dq = (rd_vref - 15300) / 521;
+		}
 		vref_mode_ac = 0x6;
 		vref_value_ac = 0x1f;
 		mode_sel = 0x6;
@@ -770,7 +779,7 @@  static void set_ds_odt(const struct chan_info *chan,
 	/* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
 	clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
 
-	phy_io_config(chan, params);
+	phy_io_config(chan, params, mr5);
 }
 
 static void pctl_start(struct dram_info *dram, u8 channel)