From patchwork Tue Jul 16 15:14:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dong Aisheng X-Patchwork-Id: 11046359 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3EBBF1510 for ; Tue, 16 Jul 2019 15:40:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2C1E8285CE for ; Tue, 16 Jul 2019 15:40:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1F0E02861D; Tue, 16 Jul 2019 15:40:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2A03D285A4 for ; Tue, 16 Jul 2019 15:40:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=u4ALEeNw9sbdYNNLuNWFzH2tGJT9CiN/o+9Tlcw0aYU=; b=UaXSjuxd9qE4ifDZMi7ojkz0Zs tcEb7vuQ5NSG1p3suis8mmB3OGhQtg9K2dIX40D3e61Es93eekA2GMOCm3gXuAMFbbzIFliz0elk1 BCHG/Uhd9dWLdLtxAuC+C4fwi9jzlJGK80LW7odOJteV3qD6QqBSW6cEjka8wNCwMsigOaj6omAD3 54noLaEXCeEwvTmKjJaQ6L3V8th7ETGP7+3N7+maCQl6NN+vOLDgZM3QWbdGq9bxWMFjs3FMVBjp0 8NzcUTTgiP6ViXf7jzuqurqEH6BkQIUjj5yoBTlrkK9eH0RK7YTgw7oWWnwIw+6j7K3/X5m+xj3nI jHC3LCfg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hnPYr-0008E0-S6; Tue, 16 Jul 2019 15:40:13 +0000 Received: from inva021.nxp.com ([92.121.34.21]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hnPVe-00054v-V5 for linux-arm-kernel@lists.infradead.org; Tue, 16 Jul 2019 15:36:57 +0000 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 968A4200060; Tue, 16 Jul 2019 17:36:53 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 9F5E520023D; Tue, 16 Jul 2019 17:36:47 +0200 (CEST) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id EBE9E402FF; Tue, 16 Jul 2019 23:36:38 +0800 (SGT) From: Dong Aisheng To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 08/15] arm64: dts: imx8: switch to new lpcg clock binding Date: Tue, 16 Jul 2019 23:14:42 +0800 Message-Id: <1563290089-11085-9-git-send-email-aisheng.dong@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1563290089-11085-1-git-send-email-aisheng.dong@nxp.com> References: <1563290089-11085-1-git-send-email-aisheng.dong@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190716_083655_538453_ED525DDA X-CRM114-Status: UNSURE ( 7.94 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dong Aisheng , devicetree@vger.kernel.org, dongas86@gmail.com, catalin.marinas@arm.com, will.deacon@arm.com, robh+dt@kernel.org, linux-imx@nxp.com, kernel@pengutronix.de, fabio.estevam@nxp.com, shawnguo@kernel.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP switch to new lpcg clock binding Signed-off-by: Dong Aisheng --- ChangeLog: v1->v2: split scu clock changes --- arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi | 30 ++++++++------- arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 44 +++++++++++----------- arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi | 13 ++++--- arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi | 4 -- arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi | 4 -- arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi | 4 -- 6 files changed, 46 insertions(+), 53 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi index 7dbc4db..d5374b3 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-adma.dtsi @@ -19,17 +19,11 @@ adma_subsys: bus@59000000 { clock-output-names = "dma_ipg_clk"; }; - /* LPCG clocks */ - adma_lpcg: clock-controller@59000000 { - reg = <0x59000000 0x2000000>; - #clock-cells = <1>; - }; - adma_lpuart0: serial@5a060000 { reg = <0x5a060000 0x1000>; interrupts = ; interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>; + clocks = <&uart0_lpcg 0>; clock-names = "ipg"; power-domains = <&pd IMX_SC_R_UART_0>; status = "disabled"; @@ -39,7 +33,7 @@ adma_subsys: bus@59000000 { reg = <0x5a070000 0x1000>; interrupts = ; interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>; + clocks = <&uart1_lpcg 0>; clock-names = "ipg"; power-domains = <&pd IMX_SC_R_UART_1>; status = "disabled"; @@ -49,7 +43,7 @@ adma_subsys: bus@59000000 { reg = <0x5a080000 0x1000>; interrupts = ; interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>; + clocks = <&uart2_lpcg 0>; clock-names = "ipg"; power-domains = <&pd IMX_SC_R_UART_2>; status = "disabled"; @@ -59,13 +53,14 @@ adma_subsys: bus@59000000 { reg = <0x5a090000 0x1000>; interrupts = ; interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>; + clocks = <&uart3_lpcg 0>; clock-names = "ipg"; power-domains = <&pd IMX_SC_R_UART_3>; status = "disabled"; }; uart0_lpcg: clock-controller@5a460000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5a460000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>, @@ -77,6 +72,7 @@ adma_subsys: bus@59000000 { }; uart1_lpcg: clock-controller@5a470000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5a470000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>, @@ -88,6 +84,7 @@ adma_subsys: bus@59000000 { }; uart2_lpcg: clock-controller@5a480000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5a480000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>, @@ -99,6 +96,7 @@ adma_subsys: bus@59000000 { }; uart3_lpcg: clock-controller@5a490000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5a490000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>, @@ -113,7 +111,7 @@ adma_subsys: bus@59000000 { reg = <0x5a800000 0x4000>; interrupts = ; interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; + clocks = <&i2c0_lpcg 0>; clock-names = "per"; assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; @@ -125,7 +123,7 @@ adma_subsys: bus@59000000 { reg = <0x5a810000 0x4000>; interrupts = ; interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; + clocks = <&i2c1_lpcg 0>; clock-names = "per"; assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; @@ -137,7 +135,7 @@ adma_subsys: bus@59000000 { reg = <0x5a820000 0x4000>; interrupts = ; interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; + clocks = <&i2c2_lpcg 0>; clock-names = "per"; assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; @@ -149,7 +147,7 @@ adma_subsys: bus@59000000 { reg = <0x5a830000 0x4000>; interrupts = ; interrupt-parent = <&gic>; - clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; + clocks = <&i2c3_lpcg 0>; clock-names = "per"; assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; @@ -158,6 +156,7 @@ adma_subsys: bus@59000000 { }; i2c0_lpcg: clock-controller@5ac00000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5ac00000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>, @@ -169,6 +168,7 @@ adma_subsys: bus@59000000 { }; i2c1_lpcg: clock-controller@5ac10000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5ac10000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>, @@ -180,6 +180,7 @@ adma_subsys: bus@59000000 { }; i2c2_lpcg: clock-controller@5ac20000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5ac20000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>, @@ -191,6 +192,7 @@ adma_subsys: bus@59000000 { }; i2c3_lpcg: clock-controller@5ac30000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5ac30000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>, diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index c6363de..a53e51b 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -37,9 +37,9 @@ conn_subsys: bus@5b000000 { interrupt-parent = <&gic>; interrupts = ; reg = <0x5b010000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; + clocks = <&sdhc0_lpcg 1>, + <&sdhc0_lpcg 0>, + <&sdhc0_lpcg 2>; clock-names = "ipg", "per", "ahb"; assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <200000000>; @@ -51,9 +51,9 @@ conn_subsys: bus@5b000000 { interrupt-parent = <&gic>; interrupts = ; reg = <0x5b020000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>; + clocks = <&sdhc1_lpcg 1>, + <&sdhc1_lpcg 0>, + <&sdhc1_lpcg 2>; clock-names = "ipg", "per", "ahb"; assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <200000000>; @@ -67,9 +67,9 @@ conn_subsys: bus@5b000000 { interrupt-parent = <&gic>; interrupts = ; reg = <0x5b030000 0x10000>; - clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>, - <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>; + clocks = <&sdhc2_lpcg 1>, + <&sdhc2_lpcg 0>, + <&sdhc2_lpcg 2>; clock-names = "ipg", "per", "ahb"; assigned-clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <200000000>; @@ -83,10 +83,10 @@ conn_subsys: bus@5b000000 { , , ; - clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>; + clocks = <&enet0_lpcg 3>, + <&enet0_lpcg 2>, + <&enet0_lpcg 1>, + <&enet0_lpcg 0>; clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; fsl,num-tx-queues=<3>; fsl,num-rx-queues=<3>; @@ -100,10 +100,10 @@ conn_subsys: bus@5b000000 { , , ; - clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>; + clocks = <&enet1_lpcg 3>, + <&enet1_lpcg 2>, + <&enet1_lpcg 1>, + <&enet1_lpcg 0>; clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; fsl,num-tx-queues=<3>; fsl,num-rx-queues=<3>; @@ -112,12 +112,8 @@ conn_subsys: bus@5b000000 { }; /* LPCG clocks */ - conn_lpcg: clock-controller-legacy@5b200000 { - reg = <0x5b200000 0xb0000>; - #clock-cells = <1>; - }; - sdhc0_lpcg: clock-controller@5b200000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5b200000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>, @@ -130,6 +126,7 @@ conn_subsys: bus@5b000000 { }; sdhc1_lpcg: clock-controller@5b210000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5b210000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>, @@ -142,6 +139,7 @@ conn_subsys: bus@5b000000 { }; sdhc2_lpcg: clock-controller@5b220000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5b220000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>, @@ -154,6 +152,7 @@ conn_subsys: bus@5b000000 { }; enet0_lpcg: clock-controller@5b230000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5b230000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, @@ -169,6 +168,7 @@ conn_subsys: bus@5b000000 { }; enet1_lpcg: clock-controller@5b240000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5b240000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi index 464d233..51e18e0 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi @@ -148,12 +148,8 @@ lsio_subsys: bus@5d000000 { }; /* LPCG clocks */ - lsio_lpcg: clock-controller-legacy@5d400000 { - reg = <0x5d400000 0x400000>; - #clock-cells = <1>; - }; - pwm0_lpcg: clock-controller@5d400000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d400000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, @@ -171,6 +167,7 @@ lsio_subsys: bus@5d000000 { }; pwm1_lpcg: clock-controller@5d410000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d410000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, @@ -188,6 +185,7 @@ lsio_subsys: bus@5d000000 { }; pwm2_lpcg: clock-controller@5d420000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d420000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, @@ -205,6 +203,7 @@ lsio_subsys: bus@5d000000 { }; pwm3_lpcg: clock-controller@5d430000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d430000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, @@ -222,6 +221,7 @@ lsio_subsys: bus@5d000000 { }; pwm4_lpcg: clock-controller@5d440000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d440000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, @@ -239,6 +239,7 @@ lsio_subsys: bus@5d000000 { }; pwm5_lpcg: clock-controller@5d450000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d450000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, @@ -256,6 +257,7 @@ lsio_subsys: bus@5d000000 { }; pwm6_lpcg: clock-controller@5d460000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d460000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, @@ -273,6 +275,7 @@ lsio_subsys: bus@5d000000 { }; pwm7_lpcg: clock-controller@5d470000 { + compatible = "fsl,imx8qxp-lpcg"; reg = <0x5d470000 0x10000>; #clock-cells = <1>; clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi index 5809324..c80303d 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-adma.dtsi @@ -4,10 +4,6 @@ * Dong Aisheng */ -&adma_lpcg { - compatible = "fsl,imx8qxp-lpcg-adma"; -}; - &adma_lpuart0 { compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi index ea0cd51..8dd22bd 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi @@ -4,10 +4,6 @@ * Dong Aisheng */ -&conn_lpcg { - compatible = "fsl,imx8qxp-lpcg-conn"; -}; - &usdhc1 { compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi index b02ae5d..1c3d117 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi @@ -59,7 +59,3 @@ &lsio_mu13 { compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; }; - -&lsio_lpcg { - compatible = "fsl,imx8qxp-lpcg-lsio"; -};