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mx.microsoft.com 1;spf=pass smtp.mailfrom=suse.com;dmarc=pass action=none header.from=suse.com;dkim=pass header.d=suse.com;arc=none Received: from DM6PR18MB3401.namprd18.prod.outlook.com (10.255.174.218) by DM6PR18MB3164.namprd18.prod.outlook.com (10.255.172.93) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2073.14; Tue, 16 Jul 2019 16:39:34 +0000 Received: from DM6PR18MB3401.namprd18.prod.outlook.com ([fe80::1fe:35f6:faf3:78c7]) by DM6PR18MB3401.namprd18.prod.outlook.com ([fe80::1fe:35f6:faf3:78c7%7]) with mapi id 15.20.2073.012; Tue, 16 Jul 2019 16:39:34 +0000 From: Jan Beulich To: "xen-devel@lists.xenproject.org" Thread-Topic: [PATCH v3 10/14] AMD/IOMMU: allow enabling with IRQ not yet set up Thread-Index: AQHVO/UMDuJQrxKu50asDLRP151iRw== Date: Tue, 16 Jul 2019 16:39:34 +0000 Message-ID: References: <6272c301-a905-38cf-dd1a-645f3d703241@suse.com> In-Reply-To: <6272c301-a905-38cf-dd1a-645f3d703241@suse.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: DB6P192CA0005.EURP192.PROD.OUTLOOK.COM (2603:10a6:4:b8::15) To DM6PR18MB3401.namprd18.prod.outlook.com (2603:10b6:5:1cc::26) authentication-results: spf=none (sender IP is ) smtp.mailfrom=JBeulich@suse.com; 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DIR:OUT; SFP:1102; SCL:1; SRVR:DM6PR18MB3164; H:DM6PR18MB3401.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: suse.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 7rlDc6YdhBRwSIveJ753uAnX2Vy2UMehGONGc0WYko/1lGsvhCMPWOkrpWitEMnSF5PNLjboeEsPtZhtS7dL7yPxxws5CJ8xKql6pjG4zpIBtWDC/1LXyNFDNx8GPzUx/V0nXhqdMaYwi4v1H1xrvxUY2foNf6Z2ZsWs2qIEkkuB8BhuYqyQxyIkCYyjS7hnfaLe0gFizQvmGFp5MFgsGAgTpZsvAJkgpKk5jfo95f8QC664hgC6zqJPD5v0sGJOxUbCoRBcx2WcFY7GfN0GkOu/makTa3mQvfGEWqezAGCcWGZs/1ywwmJCBnhcSU2fAo0bBTpTCqJvFwJCbIsylY6MY2YQXJd+qtd2l215O3BIVzAWuZ4E05dbIu+jis/G3O3Qab2cqtMMJckFIJa00MLdljgwfeuFhRJGsL+oc98= Content-ID: MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: de420d15-db38-4267-ee0e-08d70a0c2f1c X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Jul 2019 16:39:34.3604 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 856b813c-16e5-49a5-85ec-6f081e13b527 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: JBeulich@suse.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR18MB3164 X-OriginatorOrg: suse.com Subject: [Xen-devel] [PATCH v3 10/14] AMD/IOMMU: allow enabling with IRQ not yet set up X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Brian Woods , Suravee Suthikulpanit Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP Early enabling (to enter x2APIC mode) requires deferring of the IRQ setup. Code to actually do that setup in the x2APIC case will get added subsequently. Signed-off-by: Jan Beulich Acked-by: Andrew Cooper Acked-by: Brian Woods --- v3: Re-base. --- a/xen/drivers/passthrough/amd/iommu_init.c +++ b/xen/drivers/passthrough/amd/iommu_init.c @@ -814,7 +814,6 @@ static void amd_iommu_erratum_746_workar static void enable_iommu(struct amd_iommu *iommu) { unsigned long flags; - struct irq_desc *desc; spin_lock_irqsave(&iommu->lock, flags); @@ -834,19 +833,27 @@ static void enable_iommu(struct amd_iomm if ( iommu->features.flds.ppr_sup ) register_iommu_ppr_log_in_mmio_space(iommu); - desc = irq_to_desc(iommu->msi.irq); - spin_lock(&desc->lock); - set_msi_affinity(desc, NULL); - spin_unlock(&desc->lock); + if ( iommu->msi.irq > 0 ) + { + struct irq_desc *desc = irq_to_desc(iommu->msi.irq); + + spin_lock(&desc->lock); + set_msi_affinity(desc, NULL); + spin_unlock(&desc->lock); + } amd_iommu_msi_enable(iommu, IOMMU_CONTROL_ENABLED); set_iommu_ht_flags(iommu); set_iommu_command_buffer_control(iommu, IOMMU_CONTROL_ENABLED); - set_iommu_event_log_control(iommu, IOMMU_CONTROL_ENABLED); - if ( iommu->features.flds.ppr_sup ) - set_iommu_ppr_log_control(iommu, IOMMU_CONTROL_ENABLED); + if ( iommu->msi.irq > 0 ) + { + set_iommu_event_log_control(iommu, IOMMU_CONTROL_ENABLED); + + if ( iommu->features.flds.ppr_sup ) + set_iommu_ppr_log_control(iommu, IOMMU_CONTROL_ENABLED); + } if ( iommu->features.flds.gt_sup ) set_iommu_guest_translation_control(iommu, IOMMU_CONTROL_ENABLED);