From patchwork Wed Jul 17 02:39:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Chuang X-Patchwork-Id: 11047127 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 2587213BD for ; Wed, 17 Jul 2019 02:45:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1783E2871E for ; Wed, 17 Jul 2019 02:45:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0BFEB28720; Wed, 17 Jul 2019 02:45:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2DE172871F for ; Wed, 17 Jul 2019 02:45:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727663AbfGQCpS convert rfc822-to-8bit (ORCPT ); Tue, 16 Jul 2019 22:45:18 -0400 Received: from gli-ex.genesyslogic.com.tw ([60.251.58.171]:42091 "EHLO gli-ex.genesyslogic.com.tw" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725892AbfGQCpS (ORCPT ); Tue, 16 Jul 2019 22:45:18 -0400 X-Greylist: delayed 329 seconds by postgrey-1.27 at vger.kernel.org; Tue, 16 Jul 2019 22:45:17 EDT Received: from localhost (172.17.104.60) by Gli-CASHT02.genesyslogic.com.tw (172.17.50.60) with Microsoft SMTP Server id 14.2.347.0; Wed, 17 Jul 2019 10:39:46 +0800 From: Ben Chuang To: , CC: , , , Ben Chuang Subject: [PATCH 1/2] mmc: sdhci: Add PLL Enable support to internal clock setup Date: Wed, 17 Jul 2019 10:39:51 +0800 Message-ID: <20190717023951.5064-1-ben.chuang@genesyslogic.com.tw> X-Mailer: git-send-email 2.22.0 MIME-Version: 1.0 X-Originating-IP: [172.17.104.60] Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The GL9750 and GL9755 chipsets, and possibly others, require PLL Enable setup as part of the internal clock setup as described in 3.2.1 Internal Clock Setup Sequence of SD Host Controller Simplified Specification Version 4.20. This changes the timeouts to the new specification of 150ms for each step and is documented as safe for "prior versions which do not support PLL Enable." Signed-off-by: Ben Chuang Co-developed-by: Michael K Johnson Signed-off-by: Michael K Johnson Signed-off-by: Ben Chuang Signed-off-by: Michael K Johnson --- drivers/mmc/host/sdhci.c | 33 ++++++++++++++++++++++++--------- 1 file changed, 24 insertions(+), 9 deletions(-) -- 2.22.0 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 59acf8e3331e..fd684d7a5f15 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1636,15 +1636,11 @@ void sdhci_enable_clk(struct sdhci_host *host, u16 clk) clk |= SDHCI_CLOCK_INT_EN; sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); - /* Wait max 20 ms */ - timeout = ktime_add_ms(ktime_get(), 20); - while (1) { - bool timedout = ktime_after(ktime_get(), timeout); - - clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); - if (clk & SDHCI_CLOCK_INT_STABLE) - break; - if (timedout) { + /* Wait max 150 ms */ + timeout = ktime_add_ms(ktime_get(), 150); + while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) + & SDHCI_CLOCK_INT_STABLE)) { + if (ktime_after(ktime_get(), timeout)) { pr_err("%s: Internal clock never stabilised.\n", mmc_hostname(host->mmc)); sdhci_dumpregs(host); @@ -1653,8 +1649,27 @@ void sdhci_enable_clk(struct sdhci_host *host, u16 clk) udelay(10); } + clk |= SDHCI_CLOCK_PLL_EN; + clk &= ~SDHCI_CLOCK_INT_STABLE; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + /* Wait max 150 ms */ + timeout = ktime_add_ms(ktime_get(), 150); + while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) + & SDHCI_CLOCK_INT_STABLE)) { + if (ktime_after(ktime_get(), timeout)) { + pr_err("%s: PLL clock never stabilised.\n", + mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return; + } + udelay(10); + } + clk |= SDHCI_CLOCK_CARD_EN; sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + mdelay(1); } EXPORT_SYMBOL_GPL(sdhci_enable_clk);