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mx.microsoft.com 1;spf=pass smtp.mailfrom=suse.com;dmarc=pass action=none header.from=suse.com;dkim=pass header.d=suse.com;arc=none Received: from DM6PR18MB3401.namprd18.prod.outlook.com (10.255.174.218) by DM6PR18MB3196.namprd18.prod.outlook.com (10.255.172.205) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2073.14; Wed, 17 Jul 2019 06:34:43 +0000 Received: from DM6PR18MB3401.namprd18.prod.outlook.com ([fe80::1fe:35f6:faf3:78c7]) by DM6PR18MB3401.namprd18.prod.outlook.com ([fe80::1fe:35f6:faf3:78c7%7]) with mapi id 15.20.2073.012; Wed, 17 Jul 2019 06:34:43 +0000 From: Jan Beulich To: "xen-devel@lists.xenproject.org" Thread-Topic: [PATCH v10 04/13] x86emul: support AVX512_4FMAPS insns Thread-Index: AQHVPGm3dbsd7xBjpEC0nwsYifMQHA== Date: Wed, 17 Jul 2019 06:34:43 +0000 Message-ID: <3ae1722e-fa97-6cea-dbb4-9a08f6ab3f14@suse.com> References: <0ccca19e-7bbb-ab1e-c0bb-a568b02874e0@suse.com> In-Reply-To: <0ccca19e-7bbb-ab1e-c0bb-a568b02874e0@suse.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: DB7PR05CA0034.eurprd05.prod.outlook.com (2603:10a6:10:36::47) To DM6PR18MB3401.namprd18.prod.outlook.com (2603:10b6:5:1cc::26) authentication-results: spf=none (sender IP is ) smtp.mailfrom=JBeulich@suse.com; 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DIR:OUT; SFP:1102; SCL:1; SRVR:DM6PR18MB3196; H:DM6PR18MB3401.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: suse.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: BgcBIp5uq21PXfv+GB1/PU7uE/cail+9M5NWHAh+iMzsmdCFY2AUY++abOOtbHzxCfcrBD8UTsTd4R7k5Pgy9pPeuUDXlv/xg09UXz4iV46I+buSwJqyhGOhLWJ5jjBpSKARMiWvI/97E3kvCWNFps3cgeuCdcsjwbDMO3FMgPYuf19raWKItBWG9nZI5+Jk0u+pNWi+CmXTDWk0HHmUwam8QmdXw4h0n6A+fb8QwaUW2ekvXpEl4iEi7DK4EJzDB9D9mUcBQFtd4UBj+2SwLfqd6PSg26qyS5k/7Sq5QMVJ7d4wM4ga4svG9S6EWjFiY4LXleV4ijgtYPHN7RKCAnj+dOgLI/P9aIIp80CVIaoFQSIQmBjumGEJ8jrXqlPbnhI6I1iVxZk4K1q6BLebJCoWd/NKBwZW0uN9apS5R2Q= Content-ID: <6E953712A98BE54E96263A87847B7B53@namprd18.prod.outlook.com> MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: ef76ddbd-0b31-46e2-168e-08d70a80da68 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Jul 2019 06:34:43.3700 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 856b813c-16e5-49a5-85ec-6f081e13b527 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: JBeulich@suse.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR18MB3196 X-OriginatorOrg: suse.com Subject: [Xen-devel] [PATCH v10 04/13] x86emul: support AVX512_4FMAPS insns X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , RogerPau Monne Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP A decoder adjustment is needed here because of the current sharing of table entries between different (implied) opcode prefixes: The same major opcodes are used for vfmsub{132,213}{p,s}{s,d}, which have a different memory operand size and different Disp8 scaling. Signed-off-by: Jan Beulich Acked-by: Andrew Cooper --- v9: Re-base. Explain need for decoder special case. v8: Correct vcpu_has_*() insertion point. v7: Re-base. v6: New. --- a/tools/tests/x86_emulator/evex-disp8.c +++ b/tools/tests/x86_emulator/evex-disp8.c @@ -538,6 +538,13 @@ static const struct test avx512pf_512[] INSNX(scatterpf1q, 66, 0f38, c7, 6, vl, sd, el), }; +static const struct test avx512_4fmaps_512[] = { + INSN(4fmaddps, f2, 0f38, 9a, el_4, d, vl), + INSN(4fmaddss, f2, 0f38, 9b, el_4, d, vl), + INSN(4fnmaddps, f2, 0f38, aa, el_4, d, vl), + INSN(4fnmaddss, f2, 0f38, ab, el_4, d, vl), +}; + static const struct test avx512_bitalg_all[] = { INSN(popcnt, 66, 0f38, 54, vl, bw, vl), INSN(pshufbitqmb, 66, 0f38, 8f, vl, b, vl), @@ -941,6 +948,7 @@ void evex_disp8_test(void *instr, struct RUN(avx512er, 512); #define cpu_has_avx512pf cpu_has_avx512f RUN(avx512pf, 512); + RUN(avx512_4fmaps, 512); RUN(avx512_bitalg, all); RUN(avx512_ifma, all); RUN(avx512_vbmi, all); --- a/tools/tests/x86_emulator/test_x86_emulator.c +++ b/tools/tests/x86_emulator/test_x86_emulator.c @@ -4274,6 +4274,81 @@ int main(int argc, char **argv) } #endif + printf("%-40s", "Testing v4fmaddps 32(%ecx),%zmm4,%zmm4{%k5}..."); + if ( stack_exec && cpu_has_avx512_4fmaps ) + { + decl_insn(v4fmaddps); + static const struct { + float f[16]; + } in = {{ + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 + }}, out = {{ + 1 + 1 * 9 + 2 * 10 + 3 * 11 + 4 * 12, + 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 16 + 16 * 9 + 17 * 10 + 18 * 11 + 19 * 12 + }}; + + asm volatile ( "vmovups %1, %%zmm4\n\t" + "vbroadcastss %%xmm4, %%zmm7\n\t" + "vaddps %%zmm4, %%zmm7, %%zmm5\n\t" + "vaddps %%zmm5, %%zmm7, %%zmm6\n\t" + "vaddps %%zmm6, %%zmm7, %%zmm7\n\t" + "kmovw %2, %%k5\n" + put_insn(v4fmaddps, + "v4fmaddps 32(%0), %%zmm4, %%zmm4%{%%k5%}") + :: "c" (NULL), "m" (in), "rmk" (0x8001) ); + + set_insn(v4fmaddps); + regs.ecx = (unsigned long)∈ + rc = x86_emulate(&ctxt, &emulops); + if ( rc != X86EMUL_OKAY || !check_eip(v4fmaddps) ) + goto fail; + + asm ( "vcmpeqps %1, %%zmm4, %%k0\n\t" + "kmovw %%k0, %0" : "=g" (rc) : "m" (out) ); + if ( rc != 0xffff ) + goto fail; + printf("okay\n"); + } + else + printf("skipped\n"); + + printf("%-40s", "Testing v4fnmaddss 16(%edx),%zmm4,%zmm4{%k3}..."); + if ( stack_exec && cpu_has_avx512_4fmaps ) + { + decl_insn(v4fnmaddss); + static const struct { + float f[16]; + } in = {{ + 1, 2, 3, 4, 5, 6, 7, 8 + }}, out = {{ + 1 - 1 * 5 - 2 * 6 - 3 * 7 - 4 * 8, 2, 3, 4 + }}; + + asm volatile ( "vmovups %1, %%xmm4\n\t" + "vaddss %%xmm4, %%xmm4, %%xmm5\n\t" + "vaddss %%xmm5, %%xmm4, %%xmm6\n\t" + "vaddss %%xmm6, %%xmm4, %%xmm7\n\t" + "kmovw %2, %%k3\n" + put_insn(v4fnmaddss, + "v4fnmaddss 16(%0), %%xmm4, %%xmm4%{%%k3%}") + :: "d" (NULL), "m" (in), "rmk" (1) ); + + set_insn(v4fnmaddss); + regs.edx = (unsigned long)∈ + rc = x86_emulate(&ctxt, &emulops); + if ( rc != X86EMUL_OKAY || !check_eip(v4fnmaddss) ) + goto fail; + + asm ( "vcmpeqps %1, %%zmm4, %%k0\n\t" + "kmovw %%k0, %0" : "=g" (rc) : "m" (out) ); + if ( rc != 0xffff ) + goto fail; + printf("okay\n"); + } + else + printf("skipped\n"); + #undef decl_insn #undef put_insn #undef set_insn --- a/tools/tests/x86_emulator/x86-emulate.h +++ b/tools/tests/x86_emulator/x86-emulate.h @@ -146,6 +146,7 @@ static inline bool xcr0_mask(uint64_t ma #define cpu_has_avx512_vbmi2 (cp.feat.avx512_vbmi2 && xcr0_mask(0xe6)) #define cpu_has_avx512_bitalg (cp.feat.avx512_bitalg && xcr0_mask(0xe6)) #define cpu_has_avx512_vpopcntdq (cp.feat.avx512_vpopcntdq && xcr0_mask(0xe6)) +#define cpu_has_avx512_4fmaps (cp.feat.avx512_4fmaps && xcr0_mask(0xe6)) #define cpu_has_xgetbv1 (cpu_has_xsave && cp.xstate.xgetbv1) --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -1892,6 +1892,7 @@ in_protmode( #define vcpu_has_avx512_bitalg() (ctxt->cpuid->feat.avx512_bitalg) #define vcpu_has_avx512_vpopcntdq() (ctxt->cpuid->feat.avx512_vpopcntdq) #define vcpu_has_rdpid() (ctxt->cpuid->feat.rdpid) +#define vcpu_has_avx512_4fmaps() (ctxt->cpuid->feat.avx512_4fmaps) #define vcpu_must_have(feat) \ generate_exception_if(!vcpu_has_##feat(), EXC_UD) @@ -3173,6 +3174,18 @@ x86_decode( state); state->simd_size = simd_other; } + + switch ( b ) + { + /* v4f{,n}madd{p,s}s need special casing */ + case 0x9a: case 0x9b: case 0xaa: case 0xab: + if ( evex.pfx == vex_f2 ) + { + disp8scale = 4; + state->simd_size = simd_128; + } + break; + } } break; @@ -9370,6 +9383,24 @@ x86_emulate( avx512_vlen_check(true); goto simd_zmm; + case X86EMUL_OPC_EVEX_F2(0x0f38, 0x9a): /* v4fmaddps m128,zmm+3,zmm{k} */ + case X86EMUL_OPC_EVEX_F2(0x0f38, 0xaa): /* v4fnmaddps m128,zmm+3,zmm{k} */ + host_and_vcpu_must_have(avx512_4fmaps); + generate_exception_if((ea.type != OP_MEM || evex.w || evex.brs || + evex.lr != 2), + EXC_UD); + op_mask = op_mask & 0xffff ? 0xf : 0; + goto simd_zmm; + + case X86EMUL_OPC_EVEX_F2(0x0f38, 0x9b): /* v4fmaddss m128,xmm+3,xmm{k} */ + case X86EMUL_OPC_EVEX_F2(0x0f38, 0xab): /* v4fnmaddss m128,xmm+3,xmm{k} */ + host_and_vcpu_must_have(avx512_4fmaps); + generate_exception_if((ea.type != OP_MEM || evex.w || evex.brs || + evex.lr == 3), + EXC_UD); + op_mask = op_mask & 1 ? 0xf : 0; + goto simd_zmm; + case X86EMUL_OPC_EVEX_66(0x0f38, 0xa0): /* vpscatterd{d,q} [xyz]mm,mem{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0xa1): /* vpscatterq{d,q} [xyz]mm,mem{k} */ case X86EMUL_OPC_EVEX_66(0x0f38, 0xa2): /* vscatterdp{s,d} [xyz]mm,mem{k} */ --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -119,6 +119,7 @@ #define cpu_has_itsc boot_cpu_has(X86_FEATURE_ITSC) /* CPUID level 0x00000007:0.edx */ +#define cpu_has_avx512_4fmaps boot_cpu_has(X86_FEATURE_AVX512_4FMAPS) #define cpu_has_tsx_force_abort boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) /* Synthesized. */