From patchwork Wed Jul 17 10:28:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Gupta, Anshuman" X-Patchwork-Id: 11047611 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E20771510 for ; Wed, 17 Jul 2019 10:32:42 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D13FB212D8 for ; Wed, 17 Jul 2019 10:32:42 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C581D2870E; Wed, 17 Jul 2019 10:32:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7B07A212D8 for ; Wed, 17 Jul 2019 10:32:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F04B96E116; Wed, 17 Jul 2019 10:32:41 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id BEE666E119 for ; Wed, 17 Jul 2019 10:32:38 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Jul 2019 03:32:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,274,1559545200"; d="scan'208";a="342995250" Received: from genxfsim-desktop.iind.intel.com ([10.223.74.120]) by orsmga005.jf.intel.com with ESMTP; 17 Jul 2019 03:32:36 -0700 From: Anshuman Gupta To: intel-gfx@lists.freedesktop.org Date: Wed, 17 Jul 2019 15:58:04 +0530 Message-Id: <20190717102804.27202-10-anshuman.gupta@intel.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190717102804.27202-1-anshuman.gupta@intel.com> References: <20190717102804.27202-1-anshuman.gupta@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 09/10] drm/i915/tgl:Added DC3CO counter in i915_dmc_info. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This patch exposes DC3CO counter in i915_dmc_info debugfs. Which will be useful for DC3CO validation. DMC firmware is using DMC_DEBUG3 register as DC3CO counter register on TGL, but as per B.Specs DMC_DEBUG3 is general purpose register. Cc: jani.nikula@intel.com Cc: imre.deak@intel.com Cc: animesh.manna@intel.com Signed-off-by: Anshuman Gupta --- drivers/gpu/drm/i915/i915_debugfs.c | 9 ++++++++- drivers/gpu/drm/i915/i915_reg.h | 3 +++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 4d59972e9689..b382b0b9e430 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2504,9 +2504,16 @@ static int i915_dmc_info(struct seq_file *m, void *unused) seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), CSR_VERSION_MINOR(csr->version)); - if (WARN_ON(INTEL_GEN(dev_priv) > 11)) + if (WARN_ON(INTEL_GEN(dev_priv) > 12)) goto out; + /* + * B.Spes specify that DMC_DEBUG3 is general debug register + * DMC folks uses this register for DC3CO counter for TGL + */ + if (IS_TIGERLAKE(dev_priv)) + seq_printf(m, "DC3CO count: %d\n", I915_READ(DMC_DEBUG3)); + seq_printf(m, "DC3 -> DC5 count: %d\n", I915_READ(IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT : SKL_CSR_DC3_DC5_COUNT)); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index df36d84a7a8d..68e4b78e4a64 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7265,6 +7265,9 @@ enum { #define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C) #define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038) +/* DMC DEBUG COUNTERS for TGL*/ +#define DMC_DEBUG3 _MMIO(0x101090) /*DC3CO debug counter*/ + /* interrupts */ #define DE_MASTER_IRQ_CONTROL (1 << 31) #define DE_SPRITEB_FLIP_DONE (1 << 29)