| Message ID | 20190717125739.21450-1-horms+renesas@verge.net.au (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | [PATCH/RFC,repost] arm64: dts: renesas: ebisu, draak: Limit EtherAVB to 100Mbps | expand |
Hi Simon, On 17/07/2019 13:57, Simon Horman wrote: > * According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of > August 24, 2018, the TX clock internal delay mode isn't supported > on R-Car E3 (r8a77990) and D3 (r8a77995). > > * TX clock internal delay mode is required for reliable 1Gbps communication > using the KSZ9031RNX phy present on the Ebisu and Draak boards. > > Thus, the E3 based Ebisu and D3 based Draak boards reliably use 1Gbps and > the speed should be limited to 100Mbps. I believe you might mean 'can not' reliable use 1Gbps here :-) Regards Kieran > > Based on work by Kazuya Mizuguchi. > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au> > > --- > > This is a repost of this change. > > In earlier review Andrew Lunn suggested that we may be able to take a > different approach to this problem by using delays provided by the > KSZ9031RNX PHY. In particular MMD address 2h, Register 8h - > RGMII Clock Pad Skew. > > I have consulted with Renesas regarding this suggestion, however, > unfortunately it appears that the delays provided by this solution > would be insufficient to allow for reliable 1Gbps communication. > > At this point I believe the safest option is to apply this patch. > --- > arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 1 + > arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts > index 83fc13ac3fa1..3d3d6d438a05 100644 > --- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts > +++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts > @@ -271,6 +271,7 @@ > interrupt-parent = <&gpio2>; > interrupts = <21 IRQ_TYPE_LEVEL_LOW>; > reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; > + max-speed = <100>; > }; > }; > > diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts > index 0711170b26b1..eb153323ed13 100644 > --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts > +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts > @@ -175,6 +175,7 @@ > reg = <0>; > interrupt-parent = <&gpio5>; > interrupts = <19 IRQ_TYPE_LEVEL_LOW>; > + max-speed = <100>; > }; > }; > >
On Wed, Jul 17, 2019 at 02:57:39PM +0200, Simon Horman wrote: > * According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of > August 24, 2018, the TX clock internal delay mode isn't supported > on R-Car E3 (r8a77990) and D3 (r8a77995). > > * TX clock internal delay mode is required for reliable 1Gbps communication > using the KSZ9031RNX phy present on the Ebisu and Draak boards. > > Thus, the E3 based Ebisu and D3 based Draak boards reliably use 1Gbps and > the speed should be limited to 100Mbps. > > Based on work by Kazuya Mizuguchi. > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au> What about adding a short comment explaining the situation?
On Wed, Jul 17, 2019 at 03:26:07PM +0200, Wolfram Sang wrote: > On Wed, Jul 17, 2019 at 02:57:39PM +0200, Simon Horman wrote: > > * According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of > > August 24, 2018, the TX clock internal delay mode isn't supported > > on R-Car E3 (r8a77990) and D3 (r8a77995). > > > > * TX clock internal delay mode is required for reliable 1Gbps communication > > using the KSZ9031RNX phy present on the Ebisu and Draak boards. > > > > Thus, the E3 based Ebisu and D3 based Draak boards reliably use 1Gbps and > > the speed should be limited to 100Mbps. > > > > Based on work by Kazuya Mizuguchi. > > > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au> > > What about adding a short comment explaining the situation? Do you mean in the DT itself?
On Wed, Jul 17, 2019 at 02:24:51PM +0100, Kieran Bingham wrote: > Hi Simon, > > On 17/07/2019 13:57, Simon Horman wrote: > > * According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of > > August 24, 2018, the TX clock internal delay mode isn't supported > > on R-Car E3 (r8a77990) and D3 (r8a77995). > > > > * TX clock internal delay mode is required for reliable 1Gbps communication > > using the KSZ9031RNX phy present on the Ebisu and Draak boards. > > > > Thus, the E3 based Ebisu and D3 based Draak boards reliably use 1Gbps and > > the speed should be limited to 100Mbps. > > I believe you might mean 'can not' reliable use 1Gbps here :-) Yes, indeed. Thanks for noticing.
> > What about adding a short comment explaining the situation? > > Do you mean in the DT itself? Yes, so we don't forget why it is there. Or do you think this is not needed? I'd think it is useful but won't insist.
On Wed, Jul 24, 2019 at 11:04:41PM +0200, Wolfram Sang wrote: > > > > What about adding a short comment explaining the situation? > > > > Do you mean in the DT itself? > > Yes, so we don't forget why it is there. Or do you think this is not > needed? I'd think it is useful but won't insist. Sure, how about something like this: /* TX clock internal delay mode is required for reliable * 1Gbps communication using the KSZ9031RNX phy present on * the Ebisu board, however, TX clock internal delay mode * isn't supported on r8a77990. Thus, limit speed to * 100Mbps for reliable communication. */ max-speed = <100>;
> Sure, how about something like this: > > /* TX clock internal delay mode is required for reliable > * 1Gbps communication using the KSZ9031RNX phy present on > * the Ebisu board, however, TX clock internal delay mode > * isn't supported on r8a77990. Thus, limit speed to > * 100Mbps for reliable communication. > */ > max-speed = <100>; Yes, I like it. If DTs have kernel coding style, there should be a blank '/*' at the beginning.
On 25 July 2019 09:35:30 CEST, Wolfram Sang <wsa@the-dreams.de> wrote: > >> Sure, how about something like this: >> >> /* TX clock internal delay mode is required for >reliable >> * 1Gbps communication using the KSZ9031RNX phy >present on >> * the Ebisu board, however, TX clock internal delay >mode >> * isn't supported on r8a77990. Thus, limit speed to >> * 100Mbps for reliable communication. >> */ >> max-speed = <100>; > >Yes, I like it. If DTs have kernel coding style, there should be a >blank >'/*' at the beginning. Thanks, I'll fix that.
diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts index 83fc13ac3fa1..3d3d6d438a05 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts +++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts @@ -271,6 +271,7 @@ interrupt-parent = <&gpio2>; interrupts = <21 IRQ_TYPE_LEVEL_LOW>; reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; + max-speed = <100>; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts index 0711170b26b1..eb153323ed13 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts @@ -175,6 +175,7 @@ reg = <0>; interrupt-parent = <&gpio5>; interrupts = <19 IRQ_TYPE_LEVEL_LOW>; + max-speed = <100>; }; };
* According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of August 24, 2018, the TX clock internal delay mode isn't supported on R-Car E3 (r8a77990) and D3 (r8a77995). * TX clock internal delay mode is required for reliable 1Gbps communication using the KSZ9031RNX phy present on the Ebisu and Draak boards. Thus, the E3 based Ebisu and D3 based Draak boards reliably use 1Gbps and the speed should be limited to 100Mbps. Based on work by Kazuya Mizuguchi. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> --- This is a repost of this change. In earlier review Andrew Lunn suggested that we may be able to take a different approach to this problem by using delays provided by the KSZ9031RNX PHY. In particular MMD address 2h, Register 8h - RGMII Clock Pad Skew. I have consulted with Renesas regarding this suggestion, however, unfortunately it appears that the delays provided by this solution would be insufficient to allow for reliable 1Gbps communication. At this point I believe the safest option is to apply this patch. --- arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 1 + arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 1 + 2 files changed, 2 insertions(+)