[v2,05/10] drm/i915/tgl:Added helper function to prefer dc3co over dc5.
diff mbox series

Message ID 20190717140949.29329-6-anshuman.gupta@intel.com
State New
Headers show
Series
  • DC3CO Support for TGL.
Related show

Commit Message

Gupta, Anshuman July 17, 2019, 2:09 p.m. UTC
This patch check if it is only edp display connected and
crtc has psr2 capability, then it sets the prefer_dc3co flag to
true. It also enable DC3CO PSR2 transcoder early exitline event
in haswell_crtc_enable() function.

TODO: B. Specs says dc3co should be allow only in video playback
case, currently driver doesn't differentiate between video playback
and a normal flip.
User space will be the best to judge if it is VPB case
otherwise we need to have that intelligence in driver.

Cc: jani.nikula@intel.com
Cc: imre.deak@intel.com
Cc: animesh.manna@intel.com
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  |  5 +
 .../drm/i915/display/intel_display_power.c    | 93 +++++++++++++++++++
 .../drm/i915/display/intel_display_power.h    |  5 +
 drivers/gpu/drm/i915/i915_drv.h               |  1 +
 drivers/gpu/drm/i915/intel_pm.c               |  2 +-
 drivers/gpu/drm/i915/intel_pm.h               |  2 +
 6 files changed, 107 insertions(+), 1 deletion(-)

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 8ab6aef4a67c..ff2865e94c4c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6447,6 +6447,9 @@  static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 
 	if (WARN_ON(intel_crtc->active))
 		return;
+	/* Enable PSR2 transcoder exit line */
+	if (pipe_config->has_psr2 && dev_priv->csr.prefer_dc3co)
+		tgl_enable_psr2_transcoder_exitline(pipe_config);
 
 	intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
 
@@ -13667,6 +13670,8 @@  static int intel_atomic_check(struct drm_device *dev,
 				       "[modeset]" : "[fastset]");
 	}
 
+	tgl_prefer_dc3co_over_dc5_check(dev_priv, state);
+
 	return 0;
 
  fail:
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 1bd5959c1dbb..62d68e21d5fa 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -18,6 +18,7 @@ 
 #include "intel_hotplug.h"
 #include "intel_sideband.h"
 #include "intel_tc.h"
+#include "intel_pm.h"
 
 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
 					 enum i915_power_well_id power_well_id);
@@ -788,6 +789,98 @@  static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
 	dev_priv->csr.dc_state = val & mask;
 }
 
+void tgl_enable_psr2_transcoder_exitline(struct intel_crtc_state  *cstate)
+{
+	u32 linetime_us, val, exit_scanlines;
+	u32 crtc_vdisplay = cstate->base.adjusted_mode.crtc_vdisplay;
+	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
+
+	if (WARN_ON(cstate->cpu_transcoder != TRANSCODER_A))
+		return;
+
+	linetime_us = fixed16_to_u32_round_up(intel_get_linetime_us(cstate));
+	if (WARN_ON(!linetime_us))
+		return;
+	/*
+	 * DC3CO Exit time 200us B.Spec 49196
+	 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
+	 * Exit line event need to program above calculated scan lines before
+	 * next VBLANK.
+	 */
+	exit_scanlines = DIV_ROUND_UP(200, linetime_us) + 1;
+	if (WARN_ON(exit_scanlines > crtc_vdisplay))
+		return;
+
+	exit_scanlines = crtc_vdisplay - exit_scanlines;
+	exit_scanlines <<= EXITLINE_SHIFT;
+	val = I915_READ(EXITLINE(cstate->cpu_transcoder));
+	val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
+	val |= exit_scanlines;
+	val |= EXITLINE_ENABLE;
+	I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
+}
+
+static bool tgl_is_only_edp_connected(struct intel_crtc_state  *crtc_state)
+{
+	struct drm_atomic_state *state = crtc_state->base.state;
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_connector *connector, *edp_connector = NULL;
+	struct drm_connector_state *connector_state;
+	int i;
+
+	for_each_new_connector_in_state(state, connector, connector_state, i) {
+		if (connector_state->crtc != &crtc->base)
+			continue;
+
+		if (connector->status == connector_status_connected &&
+		    connector->connector_type != DRM_MODE_CONNECTOR_eDP)
+			return false;
+		else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP &&
+			 connector->status == connector_status_connected)
+			edp_connector = connector;
+	}
+
+	if (edp_connector)
+		return true;
+
+	return false;
+}
+
+/*
+ * tgl_prefer_dc3co_over_dc5_check check whether it is worth to choose
+ * DC3CO over DC5. Currently it just check crtc psr2 capebilty and only
+ * edp display should be connected.
+ * TODO: Prefer DC3CO over DC5 only in video playback.
+ */
+void tgl_prefer_dc3co_over_dc5_check(struct drm_i915_private *dev_priv,
+				     struct intel_atomic_state *state)
+{
+	struct intel_crtc_state *crtc_state;
+	struct intel_crtc *crtc;
+	int i;
+
+	dev_priv->csr.prefer_dc3co = false;
+
+	if (!IS_TIGERLAKE(dev_priv))
+		return;
+
+	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
+		if (!crtc_state->has_psr2 && crtc_state->base.active) {
+			dev_priv->csr.prefer_dc3co = false;
+			return;
+		} else if (crtc_state->has_psr2) {
+			if (tgl_is_only_edp_connected(crtc_state) &&
+			    crtc_state->base.active) {
+				dev_priv->csr.prefer_dc3co = true;
+				continue;
+			} else {
+				dev_priv->csr.prefer_dc3co = false;
+				return;
+			}
+		}
+	}
+}
+
 static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
 {
 	gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index ebb397e330ea..93ee08de7b06 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -12,6 +12,8 @@ 
 
 struct drm_i915_private;
 struct intel_encoder;
+struct intel_crtc_state;
+struct intel_atomic_state;
 
 enum intel_display_power_domain {
 	POWER_DOMAIN_DISPLAY_CORE,
@@ -252,6 +254,9 @@  void hsw_enable_pc8(struct drm_i915_private *dev_priv);
 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
+void tgl_prefer_dc3co_over_dc5_check(struct drm_i915_private *dev_priv,
+				     struct intel_atomic_state *state);
+void tgl_enable_psr2_transcoder_exitline(struct intel_crtc_state  *cstate);
 
 const char *
 intel_display_power_domain_str(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 37d07a91b385..4f444718cd1f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -359,6 +359,7 @@  struct intel_csr {
 	u32 dc_state;
 	u32 allowed_dc_mask;
 	intel_wakeref_t wakeref;
+	bool prefer_dc3co;
 };
 
 enum i915_cache_level {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 0cecea228546..b1ce0a443761 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4583,7 +4583,7 @@  skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency,
 	return ret;
 }
 
-static uint_fixed_16_16_t
+uint_fixed_16_16_t
 intel_get_linetime_us(const struct intel_crtc_state *crtc_state)
 {
 	u32 pixel_rate;
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index e3573e1e16e3..454e92c06dff 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -8,6 +8,7 @@ 
 
 #include <linux/types.h>
 
+#include "i915_drv.h"
 #include "i915_reg.h"
 
 struct drm_device;
@@ -76,6 +77,7 @@  u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv, i915_reg_t reg);
 u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, i915_reg_t reg);
 
 u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
+uint_fixed_16_16_t intel_get_linetime_us(const struct intel_crtc_state *cstate);
 
 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
 unsigned long i915_mch_val(struct drm_i915_private *dev_priv);