[v6,12/14] crypto: caam - force DMA address to 32-bit on 64-bit i.MX SoCs
diff mbox series

Message ID 20190717152458.22337-13-andrew.smirnov@gmail.com
State Changes Requested
Delegated to: Herbert Xu
Headers show
Series
  • crypto: caam - Add i.MX8MQ support
Related show

Commit Message

Andrey Smirnov July 17, 2019, 3:24 p.m. UTC
i.MX8 SoC still use 32-bit addresses in its CAAM implmentation, so
change all of the code to be able to handle that.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Cc: Chris Spencer <christopher.spencer@sea.co.uk>
Cc: Cory Tusar <cory.tusar@zii.aero>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Horia Geantă <horia.geanta@nxp.com>
Cc: Aymen Sghaier <aymen.sghaier@nxp.com>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: linux-crypto@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
 drivers/crypto/caam/caampkc.c     |  8 +++----
 drivers/crypto/caam/ctrl.c        |  6 +++--
 drivers/crypto/caam/desc_constr.h | 10 ++++++--
 drivers/crypto/caam/intern.h      |  2 +-
 drivers/crypto/caam/pdb.h         | 16 +++++++++----
 drivers/crypto/caam/pkc_desc.c    |  8 +++----
 drivers/crypto/caam/regs.h        | 39 +++++++++++++++++++++++--------
 7 files changed, 62 insertions(+), 27 deletions(-)

Comments

Horia Geanta Aug. 5, 2019, 8:23 a.m. UTC | #1
On 7/17/2019 6:25 PM, Andrey Smirnov wrote:
> i.MX8 SoC still use 32-bit addresses in its CAAM implmentation, so
i.MX8 SoC or i.MX8 mScale?
Looking at the documentation, some i.MX8 parts (for e.g. QM and QXP)
allow for 36-bit addresses.

> change all of the code to be able to handle that.
> 
Shouldn't this case (32-bit CAAM and CONFIG_ARCH_DMA_ADDR_T_64BIT=y) work
for any ARMv8 SoC, i.e. how is this i.MX-specific?

> @@ -603,11 +603,13 @@ static int caam_probe(struct platform_device *pdev)
>  		ret = init_clocks(dev, ctrlpriv, imx_soc_match->data);
>  		if (ret)
>  			return ret;
> +
> +		caam_ptr_sz = sizeof(u32);
> +	} else {
> +		caam_ptr_sz = sizeof(dma_addr_t);
caam_ptr_sz should be deduced by reading MCFGR[PS] bit, i.e. decoupled
from dma_addr_t.

There is another configuration that should be considered
(even though highly unlikely):
caam_ptr_sz=1  - > 32-bit addresses for CAAM
CONFIG_ARCH_DMA_ADDR_T_64BIT=n - 32-bit dma_addr_t
so the logic has to be carefully evaluated.

> @@ -191,7 +191,8 @@ static inline u64 caam_dma64_to_cpu(u64 value)
>  
>  static inline u64 cpu_to_caam_dma(u64 value)
>  {
> -	if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
> +	if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) &&
> +	    !caam_imx)
Related to my previous comment (i.MX-specific vs. SoC-generic),
this should probably change to smth. like: caam_ptr_sz == sizeof(u64)

>  		return cpu_to_caam_dma64(value);
>  	else
>  		return cpu_to_caam32(value);
> @@ -199,7 +200,8 @@ static inline u64 cpu_to_caam_dma(u64 value)
>  
>  static inline u64 caam_dma_to_cpu(u64 value)
>  {
> -	if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
> +	if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) &&
> +	    !caam_imx)
Same here.

>  		return caam_dma64_to_cpu(value);
>  	else
>  		return caam32_to_cpu(value);
> @@ -213,13 +215,24 @@ static inline u64 caam_dma_to_cpu(u64 value)
>  static inline void jr_outentry_get(void *outring, int hw_idx, dma_addr_t *desc,
>  				   u32 *jrstatus)
>  {
> -	struct {
> -		dma_addr_t desc;/* Pointer to completed descriptor */
> -		u32 jrstatus;	/* Status for completed descriptor */
> -	} __packed *outentry = outring;
>  
> -	*desc = outentry[hw_idx].desc;
> -	*jrstatus = outentry[hw_idx].jrstatus;
> +	if (caam_imx) {
Same here: if (caam_ptr_sz == sizeof(u32))

> +		struct {
> +			u32 desc;
> +			u32 jrstatus;
> +		} __packed *outentry = outring;
> +
> +		*desc = outentry[hw_idx].desc;
> +		*jrstatus = outentry[hw_idx].jrstatus;
> +	} else {
> +		struct {
> +			dma_addr_t desc;/* Pointer to completed descriptor */
> +			u32 jrstatus;	/* Status for completed descriptor */
> +		} __packed *outentry = outring;
> +
> +		*desc = outentry[hw_idx].desc;
> +		*jrstatus = outentry[hw_idx].jrstatus;
> +	}
>  }
>  
>  #define SIZEOF_JR_OUTENTRY	(caam_ptr_sz + sizeof(u32))
> @@ -246,9 +259,15 @@ static inline u32 jr_outentry_jrstatus(void *outring, int hw_idx)
>  
>  static inline void jr_inpentry_set(void *inpring, int hw_idx, dma_addr_t val)
>  {
> -	dma_addr_t *inpentry = inpring;
> +	if (caam_imx) {
And here: if (caam_ptr_sz == sizeof(u32))

> +		u32 *inpentry = inpring;
>  
> -	inpentry[hw_idx] = val;
> +		inpentry[hw_idx] = val;
> +	} else {
> +		dma_addr_t *inpentry = inpring;
> +
> +		inpentry[hw_idx] = val;
> +	}
>  }

Horia
Andrey Smirnov Aug. 12, 2019, 7:27 p.m. UTC | #2
On Mon, Aug 5, 2019 at 1:23 AM Horia Geanta <horia.geanta@nxp.com> wrote:
>
> On 7/17/2019 6:25 PM, Andrey Smirnov wrote:
> > i.MX8 SoC still use 32-bit addresses in its CAAM implmentation, so
> i.MX8 SoC or i.MX8 mScale?
> Looking at the documentation, some i.MX8 parts (for e.g. QM and QXP)
> allow for 36-bit addresses.
>

mScale. Will update the message.

> > change all of the code to be able to handle that.
> >
> Shouldn't this case (32-bit CAAM and CONFIG_ARCH_DMA_ADDR_T_64BIT=y) work
> for any ARMv8 SoC, i.e. how is this i.MX-specific?
>

It's a generic change.

> > @@ -603,11 +603,13 @@ static int caam_probe(struct platform_device *pdev)
> >               ret = init_clocks(dev, ctrlpriv, imx_soc_match->data);
> >               if (ret)
> >                       return ret;
> > +
> > +             caam_ptr_sz = sizeof(u32);
> > +     } else {
> > +             caam_ptr_sz = sizeof(dma_addr_t);
> caam_ptr_sz should be deduced by reading MCFGR[PS] bit, i.e. decoupled
> from dma_addr_t.
>

MCFGR[PS] is not mentioned in i.MX8MQ SRM and MCFG_PS in CTPR_MS is
documented as set to "0" (seems to match in real HW as well). Doesn't
seem like a workable solution for i.MX8MQ. Is there something I am
missing?

> There is another configuration that should be considered
> (even though highly unlikely):
> caam_ptr_sz=1  - > 32-bit addresses for CAAM
> CONFIG_ARCH_DMA_ADDR_T_64BIT=n - 32-bit dma_addr_t
> so the logic has to be carefully evaluated.
>

I don't understand what you mean here. 32-bit CAAM + 32-bit dma_addr_t
should already be the case for i.MX6, etc. how is what you describe
different?

> > @@ -191,7 +191,8 @@ static inline u64 caam_dma64_to_cpu(u64 value)
> >
> >  static inline u64 cpu_to_caam_dma(u64 value)
> >  {
> > -     if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
> > +     if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) &&
> > +         !caam_imx)
> Related to my previous comment (i.MX-specific vs. SoC-generic),
> this should probably change to smth. like: caam_ptr_sz == sizeof(u64)
>

Makes sense, will do here and in other places.

Thanks,
Andrey Smirnov
Horia Geanta Aug. 13, 2019, 1:38 p.m. UTC | #3
On 8/12/2019 10:27 PM, Andrey Smirnov wrote:
> On Mon, Aug 5, 2019 at 1:23 AM Horia Geanta <horia.geanta@nxp.com> wrote:
>>
>> On 7/17/2019 6:25 PM, Andrey Smirnov wrote:
>>> @@ -603,11 +603,13 @@ static int caam_probe(struct platform_device *pdev)
>>>               ret = init_clocks(dev, ctrlpriv, imx_soc_match->data);
>>>               if (ret)
>>>                       return ret;
>>> +
>>> +             caam_ptr_sz = sizeof(u32);
>>> +     } else {
>>> +             caam_ptr_sz = sizeof(dma_addr_t);
>> caam_ptr_sz should be deduced by reading MCFGR[PS] bit, i.e. decoupled
>> from dma_addr_t.
>>
> 
> MCFGR[PS] is not mentioned in i.MX8MQ SRM and MCFG_PS in CTPR_MS is
> documented as set to "0" (seems to match in real HW as well). Doesn't
> seem like a workable solution for i.MX8MQ. Is there something I am
> missing?
> 
If CTPR_MS[PS]=0, this means CAAM does not allow choosing the "pointer size"
via MCFGR[PS]. Usually in this case the RM does not document MCFGR[PS] bit,
which is identical to MCFGR[PS]=0.

Thus the logic should be smth. like:
	caam_ptr_sz = CTPR_MS[PS] && MCFGR[PS] ? 64 : 32;

>> There is another configuration that should be considered
>> (even though highly unlikely):
>> caam_ptr_sz=1  - > 32-bit addresses for CAAM
>> CONFIG_ARCH_DMA_ADDR_T_64BIT=n - 32-bit dma_addr_t
>> so the logic has to be carefully evaluated.
>>
> 
> I don't understand what you mean here. 32-bit CAAM + 32-bit dma_addr_t
> should already be the case for i.MX6, etc. how is what you describe
> different?
> 
Sorry for not being clear.

caam_ptr_sz=1  - > 32-bit addresses for CAAM
should have been
caam_ptr_sz=*64*  - > 32-bit addresses for CAAM
i.e. CAAM address has "more than" (>) 32 bits (exact number of bits is
SoC / chassis specific) and thus will be represented on 8 bytes.

Thanks,
Horia
Andrey Smirnov Aug. 13, 2019, 6:50 p.m. UTC | #4
On Tue, Aug 13, 2019 at 6:38 AM Horia Geanta <horia.geanta@nxp.com> wrote:
>
> On 8/12/2019 10:27 PM, Andrey Smirnov wrote:
> > On Mon, Aug 5, 2019 at 1:23 AM Horia Geanta <horia.geanta@nxp.com> wrote:
> >>
> >> On 7/17/2019 6:25 PM, Andrey Smirnov wrote:
> >>> @@ -603,11 +603,13 @@ static int caam_probe(struct platform_device *pdev)
> >>>               ret = init_clocks(dev, ctrlpriv, imx_soc_match->data);
> >>>               if (ret)
> >>>                       return ret;
> >>> +
> >>> +             caam_ptr_sz = sizeof(u32);
> >>> +     } else {
> >>> +             caam_ptr_sz = sizeof(dma_addr_t);
> >> caam_ptr_sz should be deduced by reading MCFGR[PS] bit, i.e. decoupled
> >> from dma_addr_t.
> >>
> >
> > MCFGR[PS] is not mentioned in i.MX8MQ SRM and MCFG_PS in CTPR_MS is
> > documented as set to "0" (seems to match in real HW as well). Doesn't
> > seem like a workable solution for i.MX8MQ. Is there something I am
> > missing?
> >
> If CTPR_MS[PS]=0, this means CAAM does not allow choosing the "pointer size"
> via MCFGR[PS]. Usually in this case the RM does not document MCFGR[PS] bit,
> which is identical to MCFGR[PS]=0.
>
> Thus the logic should be smth. like:
>         caam_ptr_sz = CTPR_MS[PS] && MCFGR[PS] ? 64 : 32;
>

Where is PS located in MCFGR? Same as in CTPR_MS, i.e. BIT(17)?

> >> There is another configuration that should be considered
> >> (even though highly unlikely):
> >> caam_ptr_sz=1  - > 32-bit addresses for CAAM
> >> CONFIG_ARCH_DMA_ADDR_T_64BIT=n - 32-bit dma_addr_t
> >> so the logic has to be carefully evaluated.
> >>
> >
> > I don't understand what you mean here. 32-bit CAAM + 32-bit dma_addr_t
> > should already be the case for i.MX6, etc. how is what you describe
> > different?
> >
> Sorry for not being clear.
>
> caam_ptr_sz=1  - > 32-bit addresses for CAAM
> should have been
> caam_ptr_sz=*64*  - > 32-bit addresses for CAAM
> i.e. CAAM address has "more than" (>) 32 bits (exact number of bits is
> SoC / chassis specific) and thus will be represented on 8 bytes.
>

Ah, I see. Can this use-case be addressed in a separate series when
the need for it arises?

Thanks,
Andrey Smirnov

Patch
diff mbox series

diff --git a/drivers/crypto/caam/caampkc.c b/drivers/crypto/caam/caampkc.c
index 80574106af29..0e95ad555156 100644
--- a/drivers/crypto/caam/caampkc.c
+++ b/drivers/crypto/caam/caampkc.c
@@ -17,13 +17,13 @@ 
 #include "sg_sw_sec4.h"
 #include "caampkc.h"
 
-#define DESC_RSA_PUB_LEN	(2 * CAAM_CMD_SZ + sizeof(struct rsa_pub_pdb))
+#define DESC_RSA_PUB_LEN	(2 * CAAM_CMD_SZ + SIZEOF_RSA_PUB_PDB)
 #define DESC_RSA_PRIV_F1_LEN	(2 * CAAM_CMD_SZ + \
-				 sizeof(struct rsa_priv_f1_pdb))
+				 SIZEOF_RSA_PRIV_F1_PDB)
 #define DESC_RSA_PRIV_F2_LEN	(2 * CAAM_CMD_SZ + \
-				 sizeof(struct rsa_priv_f2_pdb))
+				 SIZEOF_RSA_PRIV_F2_PDB)
 #define DESC_RSA_PRIV_F3_LEN	(2 * CAAM_CMD_SZ + \
-				 sizeof(struct rsa_priv_f3_pdb))
+				 SIZEOF_RSA_PRIV_F3_PDB)
 #define CAAM_RSA_MAX_INPUT_SIZE	512 /* for a 4096-bit modulus */
 
 /* buffer filled with zeros, used for padding */
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index e5eaaf1efe45..b309535f3157 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -603,11 +603,13 @@  static int caam_probe(struct platform_device *pdev)
 		ret = init_clocks(dev, ctrlpriv, imx_soc_match->data);
 		if (ret)
 			return ret;
+
+		caam_ptr_sz = sizeof(u32);
+	} else {
+		caam_ptr_sz = sizeof(dma_addr_t);
 	}
 	caam_imx = (bool)imx_soc_match;
 
-	caam_ptr_sz = sizeof(dma_addr_t);
-
 	/* Get configuration properties from device tree */
 	/* First, get register page */
 	ctrl = of_iomap(nprop, 0);
diff --git a/drivers/crypto/caam/desc_constr.h b/drivers/crypto/caam/desc_constr.h
index 3a83a3332ba9..5602b8f192de 100644
--- a/drivers/crypto/caam/desc_constr.h
+++ b/drivers/crypto/caam/desc_constr.h
@@ -109,9 +109,15 @@  static inline void init_job_desc_pdb(u32 * const desc, u32 options,
 
 static inline void append_ptr(u32 * const desc, dma_addr_t ptr)
 {
-	dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
+	if (caam_ptr_sz == sizeof(dma_addr_t)) {
+		dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
 
-	*offset = cpu_to_caam_dma(ptr);
+		*offset = cpu_to_caam_dma(ptr);
+	} else {
+		u32 *offset = (u32 *)desc_end(desc);
+
+		*offset = cpu_to_caam_dma(ptr);
+	}
 
 	(*desc) = cpu_to_caam32(caam32_to_cpu(*desc) +
 				CAAM_PTR_SZ / CAAM_CMD_SZ);
diff --git a/drivers/crypto/caam/intern.h b/drivers/crypto/caam/intern.h
index c00c7c84ec84..731b06becd9c 100644
--- a/drivers/crypto/caam/intern.h
+++ b/drivers/crypto/caam/intern.h
@@ -219,7 +219,7 @@  static inline u64 caam_get_dma_mask(struct device *dev)
 {
 	struct device_node *nprop = dev->of_node;
 
-	if (sizeof(dma_addr_t) != sizeof(u64))
+	if (caam_ptr_sz != sizeof(u64))
 		return DMA_BIT_MASK(32);
 
 	if (caam_dpaa2)
diff --git a/drivers/crypto/caam/pdb.h b/drivers/crypto/caam/pdb.h
index 810f0bef0652..68c1fd5dee5d 100644
--- a/drivers/crypto/caam/pdb.h
+++ b/drivers/crypto/caam/pdb.h
@@ -512,7 +512,9 @@  struct rsa_pub_pdb {
 	dma_addr_t	n_dma;
 	dma_addr_t	e_dma;
 	u32		f_len;
-} __packed;
+};
+
+#define SIZEOF_RSA_PUB_PDB	(2 * sizeof(u32) + 4 * caam_ptr_sz)
 
 /**
  * RSA Decrypt PDB - Private Key Form #1
@@ -528,7 +530,9 @@  struct rsa_priv_f1_pdb {
 	dma_addr_t	f_dma;
 	dma_addr_t	n_dma;
 	dma_addr_t	d_dma;
-} __packed;
+};
+
+#define SIZEOF_RSA_PRIV_F1_PDB	(sizeof(u32) + 4 * caam_ptr_sz)
 
 /**
  * RSA Decrypt PDB - Private Key Form #2
@@ -554,7 +558,9 @@  struct rsa_priv_f2_pdb {
 	dma_addr_t	tmp1_dma;
 	dma_addr_t	tmp2_dma;
 	u32		p_q_len;
-} __packed;
+};
+
+#define SIZEOF_RSA_PRIV_F2_PDB	(2 * sizeof(u32) + 7 * caam_ptr_sz)
 
 /**
  * RSA Decrypt PDB - Private Key Form #3
@@ -586,6 +592,8 @@  struct rsa_priv_f3_pdb {
 	dma_addr_t	tmp1_dma;
 	dma_addr_t	tmp2_dma;
 	u32		p_q_len;
-} __packed;
+};
+
+#define SIZEOF_RSA_PRIV_F3_PDB	(2 * sizeof(u32) + 9 * caam_ptr_sz)
 
 #endif
diff --git a/drivers/crypto/caam/pkc_desc.c b/drivers/crypto/caam/pkc_desc.c
index 2a8d87ea94bf..0d5ee762e036 100644
--- a/drivers/crypto/caam/pkc_desc.c
+++ b/drivers/crypto/caam/pkc_desc.c
@@ -13,7 +13,7 @@ 
 /* Descriptor for RSA Public operation */
 void init_rsa_pub_desc(u32 *desc, struct rsa_pub_pdb *pdb)
 {
-	init_job_desc_pdb(desc, 0, sizeof(*pdb));
+	init_job_desc_pdb(desc, 0, SIZEOF_RSA_PUB_PDB);
 	append_cmd(desc, pdb->sgf);
 	append_ptr(desc, pdb->f_dma);
 	append_ptr(desc, pdb->g_dma);
@@ -26,7 +26,7 @@  void init_rsa_pub_desc(u32 *desc, struct rsa_pub_pdb *pdb)
 /* Descriptor for RSA Private operation - Private Key Form #1 */
 void init_rsa_priv_f1_desc(u32 *desc, struct rsa_priv_f1_pdb *pdb)
 {
-	init_job_desc_pdb(desc, 0, sizeof(*pdb));
+	init_job_desc_pdb(desc, 0, SIZEOF_RSA_PRIV_F1_PDB);
 	append_cmd(desc, pdb->sgf);
 	append_ptr(desc, pdb->g_dma);
 	append_ptr(desc, pdb->f_dma);
@@ -39,7 +39,7 @@  void init_rsa_priv_f1_desc(u32 *desc, struct rsa_priv_f1_pdb *pdb)
 /* Descriptor for RSA Private operation - Private Key Form #2 */
 void init_rsa_priv_f2_desc(u32 *desc, struct rsa_priv_f2_pdb *pdb)
 {
-	init_job_desc_pdb(desc, 0, sizeof(*pdb));
+	init_job_desc_pdb(desc, 0, SIZEOF_RSA_PRIV_F2_PDB);
 	append_cmd(desc, pdb->sgf);
 	append_ptr(desc, pdb->g_dma);
 	append_ptr(desc, pdb->f_dma);
@@ -56,7 +56,7 @@  void init_rsa_priv_f2_desc(u32 *desc, struct rsa_priv_f2_pdb *pdb)
 /* Descriptor for RSA Private operation - Private Key Form #3 */
 void init_rsa_priv_f3_desc(u32 *desc, struct rsa_priv_f3_pdb *pdb)
 {
-	init_job_desc_pdb(desc, 0, sizeof(*pdb));
+	init_job_desc_pdb(desc, 0, SIZEOF_RSA_PRIV_F3_PDB);
 	append_cmd(desc, pdb->sgf);
 	append_ptr(desc, pdb->g_dma);
 	append_ptr(desc, pdb->f_dma);
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index ec49f5ba9689..3c3ad474d08f 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -191,7 +191,8 @@  static inline u64 caam_dma64_to_cpu(u64 value)
 
 static inline u64 cpu_to_caam_dma(u64 value)
 {
-	if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
+	if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) &&
+	    !caam_imx)
 		return cpu_to_caam_dma64(value);
 	else
 		return cpu_to_caam32(value);
@@ -199,7 +200,8 @@  static inline u64 cpu_to_caam_dma(u64 value)
 
 static inline u64 caam_dma_to_cpu(u64 value)
 {
-	if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
+	if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) &&
+	    !caam_imx)
 		return caam_dma64_to_cpu(value);
 	else
 		return caam32_to_cpu(value);
@@ -213,13 +215,24 @@  static inline u64 caam_dma_to_cpu(u64 value)
 static inline void jr_outentry_get(void *outring, int hw_idx, dma_addr_t *desc,
 				   u32 *jrstatus)
 {
-	struct {
-		dma_addr_t desc;/* Pointer to completed descriptor */
-		u32 jrstatus;	/* Status for completed descriptor */
-	} __packed *outentry = outring;
 
-	*desc = outentry[hw_idx].desc;
-	*jrstatus = outentry[hw_idx].jrstatus;
+	if (caam_imx) {
+		struct {
+			u32 desc;
+			u32 jrstatus;
+		} __packed *outentry = outring;
+
+		*desc = outentry[hw_idx].desc;
+		*jrstatus = outentry[hw_idx].jrstatus;
+	} else {
+		struct {
+			dma_addr_t desc;/* Pointer to completed descriptor */
+			u32 jrstatus;	/* Status for completed descriptor */
+		} __packed *outentry = outring;
+
+		*desc = outentry[hw_idx].desc;
+		*jrstatus = outentry[hw_idx].jrstatus;
+	}
 }
 
 #define SIZEOF_JR_OUTENTRY	(caam_ptr_sz + sizeof(u32))
@@ -246,9 +259,15 @@  static inline u32 jr_outentry_jrstatus(void *outring, int hw_idx)
 
 static inline void jr_inpentry_set(void *inpring, int hw_idx, dma_addr_t val)
 {
-	dma_addr_t *inpentry = inpring;
+	if (caam_imx) {
+		u32 *inpentry = inpring;
 
-	inpentry[hw_idx] = val;
+		inpentry[hw_idx] = val;
+	} else {
+		dma_addr_t *inpentry = inpring;
+
+		inpentry[hw_idx] = val;
+	}
 }
 
 #define SIZEOF_JR_INPENTRY	caam_ptr_sz