drm/i915: Flush all user surfaces prior to first use
diff mbox series

Message ID 20190718090158.25123-1-chris@chris-wilson.co.uk
State New
Headers show
Series
  • drm/i915: Flush all user surfaces prior to first use
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Commit Message

Chris Wilson July 18, 2019, 9:01 a.m. UTC
Since userspace has the ability to bypass the CPU cache from within its
unpriviledged command stream, we have to flush the CPU cache to memory
in order to overwrite the previous contents on creation.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: stablevger.kernel.org
---
 drivers/gpu/drm/i915/gem/i915_gem_shmem.c | 25 +++++++----------------
 1 file changed, 7 insertions(+), 18 deletions(-)

Comments

Chris Wilson July 18, 2019, 1:46 p.m. UTC | #1
Quoting Patchwork (2019-07-18 14:18:45)
> == Series Details ==
> 
> Series: drm/i915: Flush all user surfaces prior to first use (rev2)
> URL   : https://patchwork.freedesktop.org/series/63871/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_6503_full -> Patchwork_13683_full
> ====================================================
> 
> Summary
> -------
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_13683_full absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_13683_full, please notify your bug team to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> Possible new issues
> -------------------
> 
>   Here are the unknown changes that may have been introduced in Patchwork_13683_full:
> 
> ### IGT changes ###
> 
> #### Possible regressions ####
> 
>   * igt@gem_pwrite@big-cpu-fbr:
>     - shard-iclb:         [PASS][1] -> [FAIL][2] +11 similar issues
>    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6503/shard-iclb3/igt@gem_pwrite@big-cpu-fbr.html
>    [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13683/shard-iclb6/igt@gem_pwrite@big-cpu-fbr.html

Oh dear, icl is behaving strangely. Yay for finding a new feature.
-Chris

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index d2a1158868e7..80e02bcdf678 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -498,24 +498,13 @@  i915_gem_object_create_shmem(struct drm_i915_private *i915, u64 size)
 	obj->write_domain = I915_GEM_DOMAIN_CPU;
 	obj->read_domains = I915_GEM_DOMAIN_CPU;
 
-	if (HAS_LLC(i915))
-		/* On some devices, we can have the GPU use the LLC (the CPU
-		 * cache) for about a 10% performance improvement
-		 * compared to uncached.  Graphics requests other than
-		 * display scanout are coherent with the CPU in
-		 * accessing this cache.  This means in this mode we
-		 * don't need to clflush on the CPU side, and on the
-		 * GPU side we only need to flush internal caches to
-		 * get data visible to the CPU.
-		 *
-		 * However, we maintain the display planes as UC, and so
-		 * need to rebind when first used as such.
-		 */
-		cache_level = I915_CACHE_LLC;
-	else
-		cache_level = I915_CACHE_NONE;
-
-	i915_gem_object_set_cache_coherency(obj, cache_level);
+	/*
+	 * Note that userspace has control over cache-bypass
+	 * via its command stream, so even on LLC architectures
+	 * we have to flush out the CPU cache to memory to
+	 * clear previous contents.
+	 */
+	i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE);
 
 	trace_i915_gem_object_create(obj);