[12/12] drm/i915: Add PIPECONF YCbCr 4:4:4 programming for ILK-IVB
diff mbox series

Message ID 20190718145053.25808-13-ville.syrjala@linux.intel.com
State New
Headers show
Series
  • drm/i915: YCbCr output fixes and prep work for YCbCr 4:4:4 output
Related show

Commit Message

Ville Syrjälä July 18, 2019, 2:50 p.m. UTC
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On ILK-IVB the pipe colorspace is configured via PIPECONF
(as opposed to PIPEMISC in BDW+). Let's configure+readout
that stuff correctly.

Enablling YCbCr 4:4:4 output will now be a simple matter of
setting crtc_state->output_format appropriately in the encoder
.compute_config(). However, when we do that we must be
aware of the fact that YCbCr DP output doesn't seem to work
on ILK (resulting image is totally garbled), but on SNB+
it works fine. However HDMI YCbCr output does work correctly
even on ILK.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 21 +++++++++++++++++++-
 drivers/gpu/drm/i915/i915_reg.h              |  4 ++++
 2 files changed, 24 insertions(+), 1 deletion(-)

Comments

Mun, Gwan-gyeong Sept. 18, 2019, 7:05 p.m. UTC | #1
On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> On ILK-IVB the pipe colorspace is configured via PIPECONF
> (as opposed to PIPEMISC in BDW+). Let's configure+readout
> that stuff correctly.
> 
> Enablling YCbCr 4:4:4 output will now be a simple matter of
Typo: Enablling -> Enabling
> setting crtc_state->output_format appropriately in the encoder
> .compute_config(). However, when we do that we must be
> aware of the fact that YCbCr DP output doesn't seem to work
> on ILK (resulting image is totally garbled), but on SNB+
> it works fine. However HDMI YCbCr output does work correctly
> even on ILK.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 21
> +++++++++++++++++++-
>  drivers/gpu/drm/i915/i915_reg.h              |  4 ++++
>  2 files changed, 24 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index bd3ff96c1618..8e98715cd63b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -9406,9 +9406,19 @@ static void ironlake_set_pipeconf(const struct
> intel_crtc_state *crtc_state)
>  	else
>  		val |= PIPECONF_PROGRESSIVE;
>  
> +	/*
> +	 * This would end up with an odd purple hue over
> +	 * the entire display. Make sure we don't do it.
> +	 */
> +	WARN_ON(crtc_state->limited_color_range &&
> +		crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
> +
>  	if (crtc_state->limited_color_range)
>  		val |= PIPECONF_COLOR_RANGE_SELECT;
>  
> +	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
> +		val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
> +
>  	val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
>  
>  	I915_WRITE(PIPECONF(pipe), val);
> @@ -9945,7 +9955,6 @@ static bool ironlake_get_pipe_config(struct
> intel_crtc *crtc,
>  	if (!wakeref)
>  		return false;
>  
> -	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>  	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
>  	pipe_config->shared_dpll = NULL;
>  
> @@ -9974,6 +9983,16 @@ static bool ironlake_get_pipe_config(struct
> intel_crtc *crtc,
>  	if (tmp & PIPECONF_COLOR_RANGE_SELECT)
>  		pipe_config->limited_color_range = true;
>  
> +	switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
> +	case PIPECONF_OUTPUT_COLORSPACE_YUV601:
> +	case PIPECONF_OUTPUT_COLORSPACE_YUV709:
> +		pipe_config->output_format =
> INTEL_OUTPUT_FORMAT_YCBCR444;
> +		break;
> +	default:
> +		pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
> +		break;
> +	}
> +
>  	pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK)
> >>
>  		PIPECONF_GAMMA_MODE_SHIFT;
>  
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 33d535ae0944..3d33a1e03a45 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5712,6 +5712,10 @@ enum {
>  #define   PIPECONF_CXSR_DOWNCLOCK	(1 << 16)
>  #define   PIPECONF_EDP_RR_MODE_SWITCH_VLV	(1 << 14)
>  #define   PIPECONF_COLOR_RANGE_SELECT	(1 << 13)
> +#define   PIPECONF_OUTPUT_COLORSPACE_MASK	(3 << 11) /* ilk-ivb */
> +#define   PIPECONF_OUTPUT_COLORSPACE_RGB	(0 << 11) /* ilk-ivb */
> +#define   PIPECONF_OUTPUT_COLORSPACE_YUV601	(1 << 11) /* ilk-ivb */
> +#define   PIPECONF_OUTPUT_COLORSPACE_YUV709	(2 << 11) /* ilk-ivb */
>  #define   PIPECONF_OUTPUT_COLORSPACE_YUV_HSW	(1 << 11) /* hsw only
> */
>  #define   PIPECONF_BPC_MASK	(0x7 << 5)
>  #define   PIPECONF_8BPC		(0 << 5)
Mun, Gwan-gyeong Sept. 20, 2019, 12:21 p.m. UTC | #2
Except typo, the changes look good to me.
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
On Wed, 2019-09-18 at 19:05 +0000, Mun, Gwan-gyeong wrote:
> On Thu, 2019-07-18 at 17:50 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > On ILK-IVB the pipe colorspace is configured via PIPECONF
> > (as opposed to PIPEMISC in BDW+). Let's configure+readout
> > that stuff correctly.
> > 
> > Enablling YCbCr 4:4:4 output will now be a simple matter of
> Typo: Enablling -> Enabling
> > setting crtc_state->output_format appropriately in the encoder
> > .compute_config(). However, when we do that we must be
> > aware of the fact that YCbCr DP output doesn't seem to work
> > on ILK (resulting image is totally garbled), but on SNB+
> > it works fine. However HDMI YCbCr output does work correctly
> > even on ILK.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 21
> > +++++++++++++++++++-
> >  drivers/gpu/drm/i915/i915_reg.h              |  4 ++++
> >  2 files changed, 24 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index bd3ff96c1618..8e98715cd63b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -9406,9 +9406,19 @@ static void ironlake_set_pipeconf(const
> > struct
> > intel_crtc_state *crtc_state)
> >  	else
> >  		val |= PIPECONF_PROGRESSIVE;
> >  
> > +	/*
> > +	 * This would end up with an odd purple hue over
> > +	 * the entire display. Make sure we don't do it.
> > +	 */
> > +	WARN_ON(crtc_state->limited_color_range &&
> > +		crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
> > +
> >  	if (crtc_state->limited_color_range)
> >  		val |= PIPECONF_COLOR_RANGE_SELECT;
> >  
> > +	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
> > +		val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
> > +
> >  	val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
> >  
> >  	I915_WRITE(PIPECONF(pipe), val);
> > @@ -9945,7 +9955,6 @@ static bool ironlake_get_pipe_config(struct
> > intel_crtc *crtc,
> >  	if (!wakeref)
> >  		return false;
> >  
> > -	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
> >  	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
> >  	pipe_config->shared_dpll = NULL;
> >  
> > @@ -9974,6 +9983,16 @@ static bool ironlake_get_pipe_config(struct
> > intel_crtc *crtc,
> >  	if (tmp & PIPECONF_COLOR_RANGE_SELECT)
> >  		pipe_config->limited_color_range = true;
> >  
> > +	switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
> > +	case PIPECONF_OUTPUT_COLORSPACE_YUV601:
> > +	case PIPECONF_OUTPUT_COLORSPACE_YUV709:
> > +		pipe_config->output_format =
> > INTEL_OUTPUT_FORMAT_YCBCR444;
> > +		break;
> > +	default:
> > +		pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
> > +		break;
> > +	}
> > +
> >  	pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK)
> >  		PIPECONF_GAMMA_MODE_SHIFT;
> >  
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index 33d535ae0944..3d33a1e03a45 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -5712,6 +5712,10 @@ enum {
> >  #define   PIPECONF_CXSR_DOWNCLOCK	(1 << 16)
> >  #define   PIPECONF_EDP_RR_MODE_SWITCH_VLV	(1 << 14)
> >  #define   PIPECONF_COLOR_RANGE_SELECT	(1 << 13)
> > +#define   PIPECONF_OUTPUT_COLORSPACE_MASK	(3 << 11) /* ilk-ivb */
> > +#define   PIPECONF_OUTPUT_COLORSPACE_RGB	(0 << 11) /* ilk-ivb */
> > +#define   PIPECONF_OUTPUT_COLORSPACE_YUV601	(1 << 11) /*
> > ilk-ivb */
> > +#define   PIPECONF_OUTPUT_COLORSPACE_YUV709	(2 << 11) /*
> > ilk-ivb */
> >  #define   PIPECONF_OUTPUT_COLORSPACE_YUV_HSW	(1 << 11) /*
> > hsw only
> > */
> >  #define   PIPECONF_BPC_MASK	(0x7 << 5)
> >  #define   PIPECONF_8BPC		(0 << 5)
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index bd3ff96c1618..8e98715cd63b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9406,9 +9406,19 @@  static void ironlake_set_pipeconf(const struct intel_crtc_state *crtc_state)
 	else
 		val |= PIPECONF_PROGRESSIVE;
 
+	/*
+	 * This would end up with an odd purple hue over
+	 * the entire display. Make sure we don't do it.
+	 */
+	WARN_ON(crtc_state->limited_color_range &&
+		crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
+
 	if (crtc_state->limited_color_range)
 		val |= PIPECONF_COLOR_RANGE_SELECT;
 
+	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
+		val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
+
 	val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
 
 	I915_WRITE(PIPECONF(pipe), val);
@@ -9945,7 +9955,6 @@  static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
 	if (!wakeref)
 		return false;
 
-	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
 	pipe_config->shared_dpll = NULL;
 
@@ -9974,6 +9983,16 @@  static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
 	if (tmp & PIPECONF_COLOR_RANGE_SELECT)
 		pipe_config->limited_color_range = true;
 
+	switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
+	case PIPECONF_OUTPUT_COLORSPACE_YUV601:
+	case PIPECONF_OUTPUT_COLORSPACE_YUV709:
+		pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
+		break;
+	default:
+		pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
+		break;
+	}
+
 	pipe_config->gamma_mode = (tmp & PIPECONF_GAMMA_MODE_MASK_ILK) >>
 		PIPECONF_GAMMA_MODE_SHIFT;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 33d535ae0944..3d33a1e03a45 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5712,6 +5712,10 @@  enum {
 #define   PIPECONF_CXSR_DOWNCLOCK	(1 << 16)
 #define   PIPECONF_EDP_RR_MODE_SWITCH_VLV	(1 << 14)
 #define   PIPECONF_COLOR_RANGE_SELECT	(1 << 13)
+#define   PIPECONF_OUTPUT_COLORSPACE_MASK	(3 << 11) /* ilk-ivb */
+#define   PIPECONF_OUTPUT_COLORSPACE_RGB	(0 << 11) /* ilk-ivb */
+#define   PIPECONF_OUTPUT_COLORSPACE_YUV601	(1 << 11) /* ilk-ivb */
+#define   PIPECONF_OUTPUT_COLORSPACE_YUV709	(2 << 11) /* ilk-ivb */
 #define   PIPECONF_OUTPUT_COLORSPACE_YUV_HSW	(1 << 11) /* hsw only */
 #define   PIPECONF_BPC_MASK	(0x7 << 5)
 #define   PIPECONF_8BPC		(0 << 5)