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DIR:OUT; SFP:1102; SCL:1; SRVR:DM6PR18MB2540; H:DM6PR18MB3401.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: suse.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: dWU70aBWfFS/HywhVK35Vz5QhSQHLBF/1rk6p8SDIu1ZOF59qaQoPRVPUr/fkfO1hw4BxIvHrEygi0OiaMODjFVbIBVQ5lN1NiACRjzNJBOusiMtNU+oHPBFOqXbqrmy3VNvhiW1Et7Hsc21Os3RkUJZtFpJE1r9kQ5UCw7gmrOJh9W/mw7AqvWo3wsdEVJlW5z9oRn14WkfdrrBWfS3CjaH7p2WCoy/vnszD78cLEKlLw7Gu0r85Vggv5+fQes1iRQrSFtLx/Lp0Wvs3NAJv+aKLJF/BaJ7KnIoejRrLMifz1j6nqzbvKt4yaN3cu8hqhZIB61XKIZJVxI6Cjxf7P7ePzPJcrXFxCxSnsrPRfVFqhA5m85LGFpIfH3/4VRts4LVUVTbUIOTbezmerhP/CatZNnEgAxncJrEodQUhjo= Content-ID: <52C2239B8BC4724684C1374403D8B075@namprd18.prod.outlook.com> MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: c35da599-08a2-4708-6a24-08d70c33ff7d X-MS-Exchange-CrossTenant-originalarrivaltime: 19 Jul 2019 10:29:36.6608 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 856b813c-16e5-49a5-85ec-6f081e13b527 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: JBeulich@suse.com X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR18MB2540 X-OriginatorOrg: suse.com Subject: [Xen-devel] [PATCH v2 2/2] x86/mtrr: Skip cache flushes on CPUs with cache self-snooping X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Andrew Cooper , Wei Liu , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Ricardo Neri Programming MTRR registers in multi-processor systems is a rather lengthy process. Furthermore, all processors must program these registers in lock step and with interrupts disabled; the process also involves flushing caches and TLBs twice. As a result, the process may take a considerable amount of time. On some platforms, this can lead to a large skew of the refined-jiffies clock source. Early when booting, if no other clock is available (e.g., booting with hpet=disabled), the refined-jiffies clock source is used to monitor the TSC clock source. If the skew of refined-jiffies is too large, Linux wrongly assumes that the TSC is unstable: clocksource: timekeeping watchdog on CPU1: Marking clocksource 'tsc-early' as unstable because the skew is too large: clocksource: 'refined-jiffies' wd_now: fffedc10 wd_last: fffedb90 mask: ffffffff clocksource: 'tsc-early' cs_now: 5eccfddebc cs_last: 5e7e3303d4 mask: ffffffffffffffff tsc: Marking TSC unstable due to clocksource watchdog As per measurements, around 98% of the time needed by the procedure to program MTRRs in multi-processor systems is spent flushing caches with wbinvd(). As per the Section 11.11.8 of the Intel 64 and IA 32 Architectures Software Developer's Manual, it is not necessary to flush caches if the CPU supports cache self-snooping. Thus, skipping the cache flushes can reduce by several tens of milliseconds the time needed to complete the programming of the MTRR registers: Platform Before After 104-core (208 Threads) Skylake 1437ms 28ms 2-core ( 4 Threads) Haswell 114ms 2ms Reported-by: Mohammad Etemadi Signed-off-by: Ricardo Neri [Linux commit fd329f276ecaad7a371d6f91b9bbea031d0c3440] Use alternatives patching instead of static_cpu_has() (which we don't have [yet]). Interestingly we've been lacking the 2nd wbinvd(), which I'm taking the liberty here. Requested-by: Andrew Cooper Signed-off-by: Jan Beulich Reviewed-by: Andrew Cooper --- v2: Re-base (use XEN_SELFSNOOP). --- a/xen/arch/x86/cpu/mtrr/generic.c +++ b/xen/arch/x86/cpu/mtrr/generic.c @@ -450,7 +450,14 @@ static bool prepare_set(void) /* Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */ write_cr0(read_cr0() | X86_CR0_CD); - wbinvd(); + + /* + * Cache flushing is the most time-consuming step when programming + * the MTRRs. Fortunately, as per the Intel Software Development + * Manual, we can skip it if the processor supports cache self- + * snooping. + */ + alternative("wbinvd", "", X86_FEATURE_XEN_SELFSNOOP); cr4 = read_cr4(); if (cr4 & X86_CR4_PGE) @@ -466,6 +473,9 @@ static bool prepare_set(void) /* Disable MTRRs, and set the default type to uncached */ mtrr_wrmsr(MSR_MTRRdefType, deftype & ~0xcff); + /* Again, only flush caches if we have to. */ + alternative("wbinvd", "", X86_FEATURE_XEN_SELFSNOOP); + return cr4 & X86_CR4_PGE; }