[2/9] drm/i915/uc: Unify uC platform check
diff mbox series

Message ID 20190722232048.9970-3-daniele.ceraolospurio@intel.com
State New
Headers show
Series
  • uC fw path unification + misc clean-up
Related show

Commit Message

Daniele Ceraolo Spurio July 22, 2019, 11:20 p.m. UTC
We have several HAS_* checks for GuC and HuC but we mostly use HAS_GUC
and HAS_HUC, with only 1 exception. Since our HW always has either
both uC or neither of them, just replace all the checks with a unified
HAS_UC.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_reset.c     |  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c |  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c |  2 +-
 drivers/gpu/drm/i915/gt/uc/intel_uc.c     |  2 +-
 drivers/gpu/drm/i915/gt/uc/selftest_guc.c |  4 ++--
 drivers/gpu/drm/i915/i915_debugfs.c       |  6 +++---
 drivers/gpu/drm/i915/i915_drv.h           | 15 ++-------------
 drivers/gpu/drm/i915/i915_gpu_error.c     |  4 ++--
 drivers/gpu/drm/i915/i915_irq.c           |  2 +-
 drivers/gpu/drm/i915/i915_pci.c           |  4 ++--
 drivers/gpu/drm/i915/intel_device_info.h  |  2 +-
 drivers/gpu/drm/i915/intel_pm.c           |  4 ++--
 drivers/gpu/drm/i915/intel_wopcm.c        |  4 ++--
 13 files changed, 21 insertions(+), 32 deletions(-)

Comments

Chris Wilson July 23, 2019, 8:21 a.m. UTC | #1
Quoting Daniele Ceraolo Spurio (2019-07-23 00:20:41)
> We have several HAS_* checks for GuC and HuC but we mostly use HAS_GUC
> and HAS_HUC, with only 1 exception. Since our HW always has either
> both uC or neither of them, just replace all the checks with a unified
> HAS_UC.
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>

Given that we only had a single .has_[hg]uc entry, calling that .has_uc
makes sense. I trust in your crystal ball that not being able to
distinguish between the availability of different uC is not important.

Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
Michal Wajdeczko July 23, 2019, 11:19 a.m. UTC | #2
On Tue, 23 Jul 2019 01:20:41 +0200, Daniele Ceraolo Spurio  
<daniele.ceraolospurio@intel.com> wrote:

> We have several HAS_* checks for GuC and HuC but we mostly use HAS_GUC
> and HAS_HUC, with only 1 exception. Since our HW always has either
> both uC or neither of them, just replace all the checks with a unified
> HAS_UC.

our hardware has also other micro-controller (DMC aka CSR) so maybe to
avoid ambiguity we shall call it HAS_GT_UC ?

on other hand our documentation mostly uses term GUC (see GEN6_GDRST)
so maybe we should not to try to diverse from that and keep using HAS_GUC?

if you insist then we can drop HAS_HUC but imho this macro was useful to
keep code clear (GuC related code was using HAS_GUC, HuC related HAS_HUC)

#define HAS_GT_UC(i915)	(INTEL_INFO(i915)->has_gt_uc)
// GuC and HuC are GT uC
#define HAS_GUC(i915)	HAS_GT_UC(i915)
#define HAS_HUC(i915)	HAS_GT_UC(i915)

and we can avoid referring to hw details where not really needed
(yes, I know, every developer should already know such hw details)

>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_reset.c     |  2 +-
>  drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c |  2 +-
>  drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c |  2 +-
>  drivers/gpu/drm/i915/gt/uc/intel_uc.c     |  2 +-
>  drivers/gpu/drm/i915/gt/uc/selftest_guc.c |  4 ++--
>  drivers/gpu/drm/i915/i915_debugfs.c       |  6 +++---
>  drivers/gpu/drm/i915/i915_drv.h           | 15 ++-------------
>  drivers/gpu/drm/i915/i915_gpu_error.c     |  4 ++--
>  drivers/gpu/drm/i915/i915_irq.c           |  2 +-
>  drivers/gpu/drm/i915/i915_pci.c           |  4 ++--
>  drivers/gpu/drm/i915/intel_device_info.h  |  2 +-
>  drivers/gpu/drm/i915/intel_pm.c           |  4 ++--
>  drivers/gpu/drm/i915/intel_wopcm.c        |  4 ++--
>  13 files changed, 21 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c  
> b/drivers/gpu/drm/i915/gt/intel_reset.c
> index 55e2ddcbd215..7fd135a5a41f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
> @@ -595,7 +595,7 @@ int intel_reset_guc(struct intel_gt *gt)
>  		INTEL_GEN(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
>  	int ret;
> -	GEM_BUG_ON(!HAS_GUC(gt->i915));
> +	GEM_BUG_ON(!HAS_UC(gt->i915));

there is "guc" in function name
there is "GUC" in bitfield name

but you are checking UC ;)

> 	intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
>  	ret = gen6_hw_domain_reset(gt, guc_domain);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c  
> b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> index 3dfa40fdbe99..ddd3b2162528 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
> @@ -80,7 +80,7 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
> 	GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
> -	if (!HAS_GUC(i915)) {
> +	if (!HAS_UC(i915)) {
>  		guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
>  		return;
>  	}
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c  
> b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> index 543854c42d9d..15891cf4bb2c 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> @@ -74,7 +74,7 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
> 	GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
> -	if (!HAS_HUC(dev_priv)) {
> +	if (!HAS_UC(dev_priv)) {
>  		huc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
>  		return;
>  	}
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c  
> b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> index 4480a3dc2449..0d50b73f6cfe 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
> @@ -61,7 +61,7 @@ static int __get_platform_enable_guc(struct intel_uc  
> *uc)
>  	struct intel_uc_fw *huc_fw = &uc->huc.fw;
>  	int enable_guc = 0;
> -	if (!HAS_GUC(uc_to_gt(uc)->i915))
> +	if (!HAS_UC(uc_to_gt(uc)->i915))
>  		return 0;
> 	/* We don't want to enable GuC/HuC on pre-Gen11 by default */
> diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c  
> b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
> index 93f7c930ab18..d1aa180050c4 100644
> --- a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
> @@ -134,7 +134,7 @@ static int igt_guc_clients(void *args)
>  	struct intel_guc *guc;
>  	int err = 0;
> -	GEM_BUG_ON(!HAS_GUC(dev_priv));
> +	GEM_BUG_ON(!HAS_UC(dev_priv));
>  	mutex_lock(&dev_priv->drm.struct_mutex);
>  	wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
> @@ -226,7 +226,7 @@ static int igt_guc_doorbells(void *arg)
>  	int i, err = 0;
>  	u16 db_id;
> -	GEM_BUG_ON(!HAS_GUC(dev_priv));
> +	GEM_BUG_ON(!HAS_UC(dev_priv));
>  	mutex_lock(&dev_priv->drm.struct_mutex);
>  	wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c  
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 6b84d04a6a28..4249107f9d0d 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1865,7 +1865,7 @@ static int i915_huc_load_status_info(struct  
> seq_file *m, void *data)
>  	intel_wakeref_t wakeref;
>  	struct drm_printer p;
> -	if (!HAS_HUC(dev_priv))
> +	if (!HAS_UC(dev_priv))
>  		return -ENODEV;
> 	p = drm_seq_file_printer(m);
> @@ -1883,7 +1883,7 @@ static int i915_guc_load_status_info(struct  
> seq_file *m, void *data)
>  	intel_wakeref_t wakeref;
>  	struct drm_printer p;
> -	if (!HAS_GUC(dev_priv))
> +	if (!HAS_UC(dev_priv))
>  		return -ENODEV;
> 	p = drm_seq_file_printer(m);
> @@ -2062,7 +2062,7 @@ static int i915_guc_log_dump(struct seq_file *m,  
> void *data)
>  	u32 *log;
>  	int i = 0;
> -	if (!HAS_GUC(dev_priv))
> +	if (!HAS_UC(dev_priv))
>  		return -ENODEV;
> 	if (dump_load_err)
> diff --git a/drivers/gpu/drm/i915/i915_drv.h  
> b/drivers/gpu/drm/i915/i915_drv.h
> index 0e44cc4b2ca1..06ddc5df12fa 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2271,20 +2271,9 @@ IS_SUBPLATFORM(const struct drm_i915_private  
> *i915,
> #define HAS_IPC(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ipc)
> -/*
> - * For now, anything with a GuC requires uCode loading, and then  
> supports
> - * command submission once loaded. But these are logically independent
> - * properties, so we have separate macros to test them.
> - */
> -#define HAS_GUC(dev_priv)	(INTEL_INFO(dev_priv)->has_guc)
> -#define HAS_GUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
> -#define HAS_GUC_SCHED(dev_priv)	(HAS_GUC(dev_priv))

yep, _UCODE and _SCHED should be nuked

> -
> -/* For now, anything with a GuC has also HuC */
> -#define HAS_HUC(dev_priv)	(HAS_GUC(dev_priv))
> -#define HAS_HUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
> +#define HAS_UC(dev_priv)	(INTEL_INFO(dev_priv)->has_uc)

time to use i915 instead of dev_priv

> -/* Having a GuC is not the same as using a GuC */
> +/* Having a uC is not the same as using a uC */
>  #define USES_GUC(dev_priv)		intel_uc_is_using_guc(&(dev_priv)->gt.uc)
>  #define  
> USES_GUC_SUBMISSION(dev_priv)	intel_uc_is_using_guc_submission(&(dev_priv)->gt.uc)
>  #define USES_HUC(dev_priv)		intel_uc_is_using_huc(&(dev_priv)->gt.uc)
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c  
> b/drivers/gpu/drm/i915/i915_gpu_error.c
> index c5b89bf4d616..1db4d7302734 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -620,7 +620,7 @@ static void err_print_uc(struct  
> drm_i915_error_state_buf *m,
>  	const struct i915_gpu_state *error =
>  		container_of(error_uc, typeof(*error), uc);
> -	if (!error->device_info.has_guc)
> +	if (!error->device_info.has_uc)
>  		return;
> 	intel_uc_fw_dump(&error_uc->guc_fw, &p);
> @@ -1557,7 +1557,7 @@ static void capture_uc_state(struct i915_gpu_state  
> *error)
>  	struct intel_uc *uc = &i915->gt.uc;
> 	/* Capturing uC state won't be useful if there is no GuC */
> -	if (!error->device_info.has_guc)
> +	if (!error->device_info.has_uc)
>  		return;
> 	error_uc->guc_fw = uc->guc.fw;
> diff --git a/drivers/gpu/drm/i915/i915_irq.c  
> b/drivers/gpu/drm/i915/i915_irq.c
> index 11c73af92597..0b2351a6c490 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -4766,7 +4766,7 @@ void intel_irq_init(struct drm_i915_private  
> *dev_priv)
>  		dev_priv->l3_parity.remap_info[i] = NULL;
> 	/* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */
> -	if (HAS_GUC_SCHED(dev_priv) && INTEL_GEN(dev_priv) < 11)
> +	if (HAS_UC(dev_priv) && INTEL_GEN(dev_priv) < 11)
>  		dev_priv->gt.pm_guc_events = GUC_INTR_GUC2HOST << 16;
> 	/* Let's track the enabled rps events */
> diff --git a/drivers/gpu/drm/i915/i915_pci.c  
> b/drivers/gpu/drm/i915/i915_pci.c
> index 40076ba431d4..b5ece92683fd 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -595,7 +595,7 @@ static const struct intel_device_info  
> intel_cherryview_info = {
>  	GEN9_DEFAULT_PAGE_SIZES, \
>  	.has_logical_ring_preemption = 1, \
>  	.display.has_csr = 1, \
> -	.has_guc = 1, \
> +	.has_uc = 1, \
>  	.display.has_ipc = 1, \
>  	.ddb_size = 896
> @@ -647,7 +647,7 @@ static const struct intel_device_info  
> intel_skylake_gt4_info = {
>  	.display.has_dp_mst = 1, \
>  	.has_logical_ring_contexts = 1, \
>  	.has_logical_ring_preemption = 1, \
> -	.has_guc = 1, \
> +	.has_uc = 1, \
>  	.ppgtt_type = INTEL_PPGTT_FULL, \
>  	.ppgtt_size = 48, \
>  	.has_reset_engine = 1, \
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h  
> b/drivers/gpu/drm/i915/intel_device_info.h
> index 45a9badc9b8e..99e5b22e26f6 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -112,7 +112,6 @@ enum intel_ppgtt_type {
>  	func(gpu_reset_clobbers_display); \
>  	func(has_reset_engine); \
>  	func(has_fpga_dbg); \
> -	func(has_guc); \
>  	func(has_l3_dpf); \
>  	func(has_llc); \
>  	func(has_logical_ring_contexts); \
> @@ -124,6 +123,7 @@ enum intel_ppgtt_type {
>  	func(has_rps); \
>  	func(has_runtime_pm); \
>  	func(has_snoop); \
> +	func(has_uc); \
>  	func(has_coherent_ggtt); \
>  	func(unfenced_needs_alignment); \
>  	func(hws_needs_physical);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c  
> b/drivers/gpu/drm/i915/intel_pm.c
> index 22472f2bd31b..53ef862731f6 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7162,7 +7162,7 @@ static void gen11_enable_rc6(struct  
> drm_i915_private *dev_priv)
>  	for_each_engine(engine, dev_priv, id)
>  		I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
> -	if (HAS_GUC(dev_priv))
> +	if (HAS_UC(dev_priv))
>  		I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
> 	I915_WRITE(GEN6_RC_SLEEP, 0);
> @@ -7243,7 +7243,7 @@ static void gen9_enable_rc6(struct  
> drm_i915_private *dev_priv)
>  	for_each_engine(engine, dev_priv, id)
>  		I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
> -	if (HAS_GUC(dev_priv))
> +	if (HAS_UC(dev_priv))
>  		I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
> 	I915_WRITE(GEN6_RC_SLEEP, 0);
> diff --git a/drivers/gpu/drm/i915/intel_wopcm.c  
> b/drivers/gpu/drm/i915/intel_wopcm.c
> index fafd4e6a1147..c966d572b0c4 100644
> --- a/drivers/gpu/drm/i915/intel_wopcm.c
> +++ b/drivers/gpu/drm/i915/intel_wopcm.c
> @@ -74,7 +74,7 @@ void intel_wopcm_init_early(struct intel_wopcm *wopcm)
>  {
>  	struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
> -	if (!HAS_GUC(i915))
> +	if (!HAS_UC(i915))
>  		return;
> 	if (INTEL_GEN(i915) >= 11)
> @@ -263,7 +263,7 @@ int intel_wopcm_init_hw(struct intel_wopcm *wopcm,  
> struct intel_gt *gt)
>  	if (!USES_GUC(i915))
>  		return 0;
> -	GEM_BUG_ON(!HAS_GUC(i915));
> +	GEM_BUG_ON(!HAS_UC(i915));

hmm, maybe

	#define HAS_WOPCM(i915)	HAS_GT_UC(i915)

and then

	GEM_BUG_ON(!HAS_WOPCM(i915));

>  	GEM_BUG_ON(!wopcm->guc.size);
>  	GEM_BUG_ON(!wopcm->guc.base);
Daniele Ceraolo Spurio July 23, 2019, 2:52 p.m. UTC | #3
On 7/23/2019 4:19 AM, Michal Wajdeczko wrote:
> On Tue, 23 Jul 2019 01:20:41 +0200, Daniele Ceraolo Spurio 
> <daniele.ceraolospurio@intel.com> wrote:
>
>> We have several HAS_* checks for GuC and HuC but we mostly use HAS_GUC
>> and HAS_HUC, with only 1 exception. Since our HW always has either
>> both uC or neither of them, just replace all the checks with a unified
>> HAS_UC.
>
> our hardware has also other micro-controller (DMC aka CSR) so maybe to
> avoid ambiguity we shall call it HAS_GT_UC ?

ack

>
> on other hand our documentation mostly uses term GUC (see GEN6_GDRST)
> so maybe we should not to try to diverse from that and keep using 
> HAS_GUC?
>
> if you insist then we can drop HAS_HUC but imho this macro was useful to
> keep code clear (GuC related code was using HAS_GUC, HuC related HAS_HUC)
>
> #define HAS_GT_UC(i915)    (INTEL_INFO(i915)->has_gt_uc)
> // GuC and HuC are GT uC
> #define HAS_GUC(i915)    HAS_GT_UC(i915)
> #define HAS_HUC(i915)    HAS_GT_UC(i915)
>
> and we can avoid referring to hw details where not really needed
> (yes, I know, every developer should already know such hw details)
>

My aim here is to unify the 2 paths around the load and just use HAS_UC 
(or HAS_GT_UC) because in the common FW functions we don't know if we're 
touching GuC or HuC. We already logically organize GuC and HuC under 
intel_uc so it should be quite evident from the code that HAS_UC 
includes them both. Mixing HAS_GT_UC in the common paths and HAS_GUC/HUC 
in the dedicated ones seems more confusing IMO.

>>
>> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
>> ---
>>  drivers/gpu/drm/i915/gt/intel_reset.c     |  2 +-
>>  drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c |  2 +-
>>  drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c |  2 +-
>>  drivers/gpu/drm/i915/gt/uc/intel_uc.c     |  2 +-
>>  drivers/gpu/drm/i915/gt/uc/selftest_guc.c |  4 ++--
>>  drivers/gpu/drm/i915/i915_debugfs.c       |  6 +++---
>>  drivers/gpu/drm/i915/i915_drv.h           | 15 ++-------------
>>  drivers/gpu/drm/i915/i915_gpu_error.c     |  4 ++--
>>  drivers/gpu/drm/i915/i915_irq.c           |  2 +-
>>  drivers/gpu/drm/i915/i915_pci.c           |  4 ++--
>>  drivers/gpu/drm/i915/intel_device_info.h  |  2 +-
>>  drivers/gpu/drm/i915/intel_pm.c           |  4 ++--
>>  drivers/gpu/drm/i915/intel_wopcm.c        |  4 ++--
>>  13 files changed, 21 insertions(+), 32 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c 
>> b/drivers/gpu/drm/i915/gt/intel_reset.c
>> index 55e2ddcbd215..7fd135a5a41f 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_reset.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_reset.c
>> @@ -595,7 +595,7 @@ int intel_reset_guc(struct intel_gt *gt)
>>          INTEL_GEN(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
>>      int ret;
>> -    GEM_BUG_ON(!HAS_GUC(gt->i915));
>> +    GEM_BUG_ON(!HAS_UC(gt->i915));
>
> there is "guc" in function name
> there is "GUC" in bitfield name
>
> but you are checking UC ;)
>

I see nothing wrong with that, we defined UC as a super-set of GUC. It's 
like e.g. HAS_DISPLAY including all display features.

>>     intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
>>      ret = gen6_hw_domain_reset(gt, guc_domain);
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c 
>> b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
>> index 3dfa40fdbe99..ddd3b2162528 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
>> @@ -80,7 +80,7 @@ static void guc_fw_select(struct intel_uc_fw *guc_fw)
>>     GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
>> -    if (!HAS_GUC(i915)) {
>> +    if (!HAS_UC(i915)) {
>>          guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
>>          return;
>>      }
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c 
>> b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
>> index 543854c42d9d..15891cf4bb2c 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
>> @@ -74,7 +74,7 @@ static void huc_fw_select(struct intel_uc_fw *huc_fw)
>>     GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
>> -    if (!HAS_HUC(dev_priv)) {
>> +    if (!HAS_UC(dev_priv)) {
>>          huc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
>>          return;
>>      }
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c 
>> b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
>> index 4480a3dc2449..0d50b73f6cfe 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
>> @@ -61,7 +61,7 @@ static int __get_platform_enable_guc(struct 
>> intel_uc *uc)
>>      struct intel_uc_fw *huc_fw = &uc->huc.fw;
>>      int enable_guc = 0;
>> -    if (!HAS_GUC(uc_to_gt(uc)->i915))
>> +    if (!HAS_UC(uc_to_gt(uc)->i915))
>>          return 0;
>>     /* We don't want to enable GuC/HuC on pre-Gen11 by default */
>> diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c 
>> b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
>> index 93f7c930ab18..d1aa180050c4 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
>> @@ -134,7 +134,7 @@ static int igt_guc_clients(void *args)
>>      struct intel_guc *guc;
>>      int err = 0;
>> -    GEM_BUG_ON(!HAS_GUC(dev_priv));
>> +    GEM_BUG_ON(!HAS_UC(dev_priv));
>>      mutex_lock(&dev_priv->drm.struct_mutex);
>>      wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
>> @@ -226,7 +226,7 @@ static int igt_guc_doorbells(void *arg)
>>      int i, err = 0;
>>      u16 db_id;
>> -    GEM_BUG_ON(!HAS_GUC(dev_priv));
>> +    GEM_BUG_ON(!HAS_UC(dev_priv));
>>      mutex_lock(&dev_priv->drm.struct_mutex);
>>      wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
>> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
>> b/drivers/gpu/drm/i915/i915_debugfs.c
>> index 6b84d04a6a28..4249107f9d0d 100644
>> --- a/drivers/gpu/drm/i915/i915_debugfs.c
>> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
>> @@ -1865,7 +1865,7 @@ static int i915_huc_load_status_info(struct 
>> seq_file *m, void *data)
>>      intel_wakeref_t wakeref;
>>      struct drm_printer p;
>> -    if (!HAS_HUC(dev_priv))
>> +    if (!HAS_UC(dev_priv))
>>          return -ENODEV;
>>     p = drm_seq_file_printer(m);
>> @@ -1883,7 +1883,7 @@ static int i915_guc_load_status_info(struct 
>> seq_file *m, void *data)
>>      intel_wakeref_t wakeref;
>>      struct drm_printer p;
>> -    if (!HAS_GUC(dev_priv))
>> +    if (!HAS_UC(dev_priv))
>>          return -ENODEV;
>>     p = drm_seq_file_printer(m);
>> @@ -2062,7 +2062,7 @@ static int i915_guc_log_dump(struct seq_file 
>> *m, void *data)
>>      u32 *log;
>>      int i = 0;
>> -    if (!HAS_GUC(dev_priv))
>> +    if (!HAS_UC(dev_priv))
>>          return -ENODEV;
>>     if (dump_load_err)
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h 
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index 0e44cc4b2ca1..06ddc5df12fa 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -2271,20 +2271,9 @@ IS_SUBPLATFORM(const struct drm_i915_private 
>> *i915,
>> #define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
>> -/*
>> - * For now, anything with a GuC requires uCode loading, and then 
>> supports
>> - * command submission once loaded. But these are logically independent
>> - * properties, so we have separate macros to test them.
>> - */
>> -#define HAS_GUC(dev_priv)    (INTEL_INFO(dev_priv)->has_guc)
>> -#define HAS_GUC_UCODE(dev_priv)    (HAS_GUC(dev_priv))
>> -#define HAS_GUC_SCHED(dev_priv)    (HAS_GUC(dev_priv))
>
> yep, _UCODE and _SCHED should be nuked
>
>> -
>> -/* For now, anything with a GuC has also HuC */
>> -#define HAS_HUC(dev_priv)    (HAS_GUC(dev_priv))
>> -#define HAS_HUC_UCODE(dev_priv)    (HAS_GUC(dev_priv))
>> +#define HAS_UC(dev_priv)    (INTEL_INFO(dev_priv)->has_uc)
>
> time to use i915 instead of dev_priv

ok

>
>> -/* Having a GuC is not the same as using a GuC */
>> +/* Having a uC is not the same as using a uC */
>>  #define USES_GUC(dev_priv) intel_uc_is_using_guc(&(dev_priv)->gt.uc)
>>  #define USES_GUC_SUBMISSION(dev_priv) 
>> intel_uc_is_using_guc_submission(&(dev_priv)->gt.uc)
>>  #define USES_HUC(dev_priv) intel_uc_is_using_huc(&(dev_priv)->gt.uc)
>> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c 
>> b/drivers/gpu/drm/i915/i915_gpu_error.c
>> index c5b89bf4d616..1db4d7302734 100644
>> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
>> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
>> @@ -620,7 +620,7 @@ static void err_print_uc(struct 
>> drm_i915_error_state_buf *m,
>>      const struct i915_gpu_state *error =
>>          container_of(error_uc, typeof(*error), uc);
>> -    if (!error->device_info.has_guc)
>> +    if (!error->device_info.has_uc)
>>          return;
>>     intel_uc_fw_dump(&error_uc->guc_fw, &p);
>> @@ -1557,7 +1557,7 @@ static void capture_uc_state(struct 
>> i915_gpu_state *error)
>>      struct intel_uc *uc = &i915->gt.uc;
>>     /* Capturing uC state won't be useful if there is no GuC */
>> -    if (!error->device_info.has_guc)
>> +    if (!error->device_info.has_uc)
>>          return;
>>     error_uc->guc_fw = uc->guc.fw;
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c 
>> b/drivers/gpu/drm/i915/i915_irq.c
>> index 11c73af92597..0b2351a6c490 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -4766,7 +4766,7 @@ void intel_irq_init(struct drm_i915_private 
>> *dev_priv)
>>          dev_priv->l3_parity.remap_info[i] = NULL;
>>     /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm 
>> reg */
>> -    if (HAS_GUC_SCHED(dev_priv) && INTEL_GEN(dev_priv) < 11)
>> +    if (HAS_UC(dev_priv) && INTEL_GEN(dev_priv) < 11)
>>          dev_priv->gt.pm_guc_events = GUC_INTR_GUC2HOST << 16;
>>     /* Let's track the enabled rps events */
>> diff --git a/drivers/gpu/drm/i915/i915_pci.c 
>> b/drivers/gpu/drm/i915/i915_pci.c
>> index 40076ba431d4..b5ece92683fd 100644
>> --- a/drivers/gpu/drm/i915/i915_pci.c
>> +++ b/drivers/gpu/drm/i915/i915_pci.c
>> @@ -595,7 +595,7 @@ static const struct intel_device_info 
>> intel_cherryview_info = {
>>      GEN9_DEFAULT_PAGE_SIZES, \
>>      .has_logical_ring_preemption = 1, \
>>      .display.has_csr = 1, \
>> -    .has_guc = 1, \
>> +    .has_uc = 1, \
>>      .display.has_ipc = 1, \
>>      .ddb_size = 896
>> @@ -647,7 +647,7 @@ static const struct intel_device_info 
>> intel_skylake_gt4_info = {
>>      .display.has_dp_mst = 1, \
>>      .has_logical_ring_contexts = 1, \
>>      .has_logical_ring_preemption = 1, \
>> -    .has_guc = 1, \
>> +    .has_uc = 1, \
>>      .ppgtt_type = INTEL_PPGTT_FULL, \
>>      .ppgtt_size = 48, \
>>      .has_reset_engine = 1, \
>> diff --git a/drivers/gpu/drm/i915/intel_device_info.h 
>> b/drivers/gpu/drm/i915/intel_device_info.h
>> index 45a9badc9b8e..99e5b22e26f6 100644
>> --- a/drivers/gpu/drm/i915/intel_device_info.h
>> +++ b/drivers/gpu/drm/i915/intel_device_info.h
>> @@ -112,7 +112,6 @@ enum intel_ppgtt_type {
>>      func(gpu_reset_clobbers_display); \
>>      func(has_reset_engine); \
>>      func(has_fpga_dbg); \
>> -    func(has_guc); \
>>      func(has_l3_dpf); \
>>      func(has_llc); \
>>      func(has_logical_ring_contexts); \
>> @@ -124,6 +123,7 @@ enum intel_ppgtt_type {
>>      func(has_rps); \
>>      func(has_runtime_pm); \
>>      func(has_snoop); \
>> +    func(has_uc); \
>>      func(has_coherent_ggtt); \
>>      func(unfenced_needs_alignment); \
>>      func(hws_needs_physical);
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c 
>> b/drivers/gpu/drm/i915/intel_pm.c
>> index 22472f2bd31b..53ef862731f6 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -7162,7 +7162,7 @@ static void gen11_enable_rc6(struct 
>> drm_i915_private *dev_priv)
>>      for_each_engine(engine, dev_priv, id)
>>          I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
>> -    if (HAS_GUC(dev_priv))
>> +    if (HAS_UC(dev_priv))
>>          I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
>>     I915_WRITE(GEN6_RC_SLEEP, 0);
>> @@ -7243,7 +7243,7 @@ static void gen9_enable_rc6(struct 
>> drm_i915_private *dev_priv)
>>      for_each_engine(engine, dev_priv, id)
>>          I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
>> -    if (HAS_GUC(dev_priv))
>> +    if (HAS_UC(dev_priv))
>>          I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
>>     I915_WRITE(GEN6_RC_SLEEP, 0);
>> diff --git a/drivers/gpu/drm/i915/intel_wopcm.c 
>> b/drivers/gpu/drm/i915/intel_wopcm.c
>> index fafd4e6a1147..c966d572b0c4 100644
>> --- a/drivers/gpu/drm/i915/intel_wopcm.c
>> +++ b/drivers/gpu/drm/i915/intel_wopcm.c
>> @@ -74,7 +74,7 @@ void intel_wopcm_init_early(struct intel_wopcm *wopcm)
>>  {
>>      struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
>> -    if (!HAS_GUC(i915))
>> +    if (!HAS_UC(i915))
>>          return;
>>     if (INTEL_GEN(i915) >= 11)
>> @@ -263,7 +263,7 @@ int intel_wopcm_init_hw(struct intel_wopcm 
>> *wopcm, struct intel_gt *gt)
>>      if (!USES_GUC(i915))
>>          return 0;
>> -    GEM_BUG_ON(!HAS_GUC(i915));
>> +    GEM_BUG_ON(!HAS_UC(i915));
>
> hmm, maybe
>
>     #define HAS_WOPCM(i915)    HAS_GT_UC(i915)

This is not technically true. The WOPCM is a piece of memory that is 
there and used on legacy platforms for non-uc things as well (e.g. the 
power ctx save/restore). That's also the reason why I haven't moved the 
wopcm under intel_uc.
What we care about here is programming the uC portion of the wopcm, 
which is why we require the uC. Once we fix the sanitizing of the 
modparam the USES_GUC() above will probably be enough and we should be 
able to drop the BUG_ON.

Daniele

>
> and then
>
>     GEM_BUG_ON(!HAS_WOPCM(i915));
>
>>      GEM_BUG_ON(!wopcm->guc.size);
>>      GEM_BUG_ON(!wopcm->guc.base);
Daniele Ceraolo Spurio July 23, 2019, 9:15 p.m. UTC | #4
<snip>

>>> -
>>> -/* For now, anything with a GuC has also HuC */
>>> -#define HAS_HUC(dev_priv)    (HAS_GUC(dev_priv))
>>> -#define HAS_HUC_UCODE(dev_priv)    (HAS_GUC(dev_priv))
>>> +#define HAS_UC(dev_priv)    (INTEL_INFO(dev_priv)->has_uc)
>>
>> time to use i915 instead of dev_priv
> 
> ok
> 

I've decided against this in the end because all the other HAS_* checks 
in the file use dev_priv and a single i915 sticks out like a sore thumb. 
Probably better to flip them all at the same time when we're ready.

Daniele

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 55e2ddcbd215..7fd135a5a41f 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -595,7 +595,7 @@  int intel_reset_guc(struct intel_gt *gt)
 		INTEL_GEN(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
 	int ret;
 
-	GEM_BUG_ON(!HAS_GUC(gt->i915));
+	GEM_BUG_ON(!HAS_UC(gt->i915));
 
 	intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
 	ret = gen6_hw_domain_reset(gt, guc_domain);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
index 3dfa40fdbe99..ddd3b2162528 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c
@@ -80,7 +80,7 @@  static void guc_fw_select(struct intel_uc_fw *guc_fw)
 
 	GEM_BUG_ON(guc_fw->type != INTEL_UC_FW_TYPE_GUC);
 
-	if (!HAS_GUC(i915)) {
+	if (!HAS_UC(i915)) {
 		guc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
 		return;
 	}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
index 543854c42d9d..15891cf4bb2c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
@@ -74,7 +74,7 @@  static void huc_fw_select(struct intel_uc_fw *huc_fw)
 
 	GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
 
-	if (!HAS_HUC(dev_priv)) {
+	if (!HAS_UC(dev_priv)) {
 		huc_fw->fetch_status = INTEL_UC_FIRMWARE_NOT_SUPPORTED;
 		return;
 	}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 4480a3dc2449..0d50b73f6cfe 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -61,7 +61,7 @@  static int __get_platform_enable_guc(struct intel_uc *uc)
 	struct intel_uc_fw *huc_fw = &uc->huc.fw;
 	int enable_guc = 0;
 
-	if (!HAS_GUC(uc_to_gt(uc)->i915))
+	if (!HAS_UC(uc_to_gt(uc)->i915))
 		return 0;
 
 	/* We don't want to enable GuC/HuC on pre-Gen11 by default */
diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
index 93f7c930ab18..d1aa180050c4 100644
--- a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
@@ -134,7 +134,7 @@  static int igt_guc_clients(void *args)
 	struct intel_guc *guc;
 	int err = 0;
 
-	GEM_BUG_ON(!HAS_GUC(dev_priv));
+	GEM_BUG_ON(!HAS_UC(dev_priv));
 	mutex_lock(&dev_priv->drm.struct_mutex);
 	wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
 
@@ -226,7 +226,7 @@  static int igt_guc_doorbells(void *arg)
 	int i, err = 0;
 	u16 db_id;
 
-	GEM_BUG_ON(!HAS_GUC(dev_priv));
+	GEM_BUG_ON(!HAS_UC(dev_priv));
 	mutex_lock(&dev_priv->drm.struct_mutex);
 	wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
 
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 6b84d04a6a28..4249107f9d0d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1865,7 +1865,7 @@  static int i915_huc_load_status_info(struct seq_file *m, void *data)
 	intel_wakeref_t wakeref;
 	struct drm_printer p;
 
-	if (!HAS_HUC(dev_priv))
+	if (!HAS_UC(dev_priv))
 		return -ENODEV;
 
 	p = drm_seq_file_printer(m);
@@ -1883,7 +1883,7 @@  static int i915_guc_load_status_info(struct seq_file *m, void *data)
 	intel_wakeref_t wakeref;
 	struct drm_printer p;
 
-	if (!HAS_GUC(dev_priv))
+	if (!HAS_UC(dev_priv))
 		return -ENODEV;
 
 	p = drm_seq_file_printer(m);
@@ -2062,7 +2062,7 @@  static int i915_guc_log_dump(struct seq_file *m, void *data)
 	u32 *log;
 	int i = 0;
 
-	if (!HAS_GUC(dev_priv))
+	if (!HAS_UC(dev_priv))
 		return -ENODEV;
 
 	if (dump_load_err)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0e44cc4b2ca1..06ddc5df12fa 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2271,20 +2271,9 @@  IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_IPC(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ipc)
 
-/*
- * For now, anything with a GuC requires uCode loading, and then supports
- * command submission once loaded. But these are logically independent
- * properties, so we have separate macros to test them.
- */
-#define HAS_GUC(dev_priv)	(INTEL_INFO(dev_priv)->has_guc)
-#define HAS_GUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
-#define HAS_GUC_SCHED(dev_priv)	(HAS_GUC(dev_priv))
-
-/* For now, anything with a GuC has also HuC */
-#define HAS_HUC(dev_priv)	(HAS_GUC(dev_priv))
-#define HAS_HUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
+#define HAS_UC(dev_priv)	(INTEL_INFO(dev_priv)->has_uc)
 
-/* Having a GuC is not the same as using a GuC */
+/* Having a uC is not the same as using a uC */
 #define USES_GUC(dev_priv)		intel_uc_is_using_guc(&(dev_priv)->gt.uc)
 #define USES_GUC_SUBMISSION(dev_priv)	intel_uc_is_using_guc_submission(&(dev_priv)->gt.uc)
 #define USES_HUC(dev_priv)		intel_uc_is_using_huc(&(dev_priv)->gt.uc)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index c5b89bf4d616..1db4d7302734 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -620,7 +620,7 @@  static void err_print_uc(struct drm_i915_error_state_buf *m,
 	const struct i915_gpu_state *error =
 		container_of(error_uc, typeof(*error), uc);
 
-	if (!error->device_info.has_guc)
+	if (!error->device_info.has_uc)
 		return;
 
 	intel_uc_fw_dump(&error_uc->guc_fw, &p);
@@ -1557,7 +1557,7 @@  static void capture_uc_state(struct i915_gpu_state *error)
 	struct intel_uc *uc = &i915->gt.uc;
 
 	/* Capturing uC state won't be useful if there is no GuC */
-	if (!error->device_info.has_guc)
+	if (!error->device_info.has_uc)
 		return;
 
 	error_uc->guc_fw = uc->guc.fw;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 11c73af92597..0b2351a6c490 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4766,7 +4766,7 @@  void intel_irq_init(struct drm_i915_private *dev_priv)
 		dev_priv->l3_parity.remap_info[i] = NULL;
 
 	/* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */
-	if (HAS_GUC_SCHED(dev_priv) && INTEL_GEN(dev_priv) < 11)
+	if (HAS_UC(dev_priv) && INTEL_GEN(dev_priv) < 11)
 		dev_priv->gt.pm_guc_events = GUC_INTR_GUC2HOST << 16;
 
 	/* Let's track the enabled rps events */
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 40076ba431d4..b5ece92683fd 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -595,7 +595,7 @@  static const struct intel_device_info intel_cherryview_info = {
 	GEN9_DEFAULT_PAGE_SIZES, \
 	.has_logical_ring_preemption = 1, \
 	.display.has_csr = 1, \
-	.has_guc = 1, \
+	.has_uc = 1, \
 	.display.has_ipc = 1, \
 	.ddb_size = 896
 
@@ -647,7 +647,7 @@  static const struct intel_device_info intel_skylake_gt4_info = {
 	.display.has_dp_mst = 1, \
 	.has_logical_ring_contexts = 1, \
 	.has_logical_ring_preemption = 1, \
-	.has_guc = 1, \
+	.has_uc = 1, \
 	.ppgtt_type = INTEL_PPGTT_FULL, \
 	.ppgtt_size = 48, \
 	.has_reset_engine = 1, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 45a9badc9b8e..99e5b22e26f6 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -112,7 +112,6 @@  enum intel_ppgtt_type {
 	func(gpu_reset_clobbers_display); \
 	func(has_reset_engine); \
 	func(has_fpga_dbg); \
-	func(has_guc); \
 	func(has_l3_dpf); \
 	func(has_llc); \
 	func(has_logical_ring_contexts); \
@@ -124,6 +123,7 @@  enum intel_ppgtt_type {
 	func(has_rps); \
 	func(has_runtime_pm); \
 	func(has_snoop); \
+	func(has_uc); \
 	func(has_coherent_ggtt); \
 	func(unfenced_needs_alignment); \
 	func(hws_needs_physical);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 22472f2bd31b..53ef862731f6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7162,7 +7162,7 @@  static void gen11_enable_rc6(struct drm_i915_private *dev_priv)
 	for_each_engine(engine, dev_priv, id)
 		I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
 
-	if (HAS_GUC(dev_priv))
+	if (HAS_UC(dev_priv))
 		I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
 
 	I915_WRITE(GEN6_RC_SLEEP, 0);
@@ -7243,7 +7243,7 @@  static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
 	for_each_engine(engine, dev_priv, id)
 		I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
 
-	if (HAS_GUC(dev_priv))
+	if (HAS_UC(dev_priv))
 		I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
 
 	I915_WRITE(GEN6_RC_SLEEP, 0);
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c
index fafd4e6a1147..c966d572b0c4 100644
--- a/drivers/gpu/drm/i915/intel_wopcm.c
+++ b/drivers/gpu/drm/i915/intel_wopcm.c
@@ -74,7 +74,7 @@  void intel_wopcm_init_early(struct intel_wopcm *wopcm)
 {
 	struct drm_i915_private *i915 = wopcm_to_i915(wopcm);
 
-	if (!HAS_GUC(i915))
+	if (!HAS_UC(i915))
 		return;
 
 	if (INTEL_GEN(i915) >= 11)
@@ -263,7 +263,7 @@  int intel_wopcm_init_hw(struct intel_wopcm *wopcm, struct intel_gt *gt)
 	if (!USES_GUC(i915))
 		return 0;
 
-	GEM_BUG_ON(!HAS_GUC(i915));
+	GEM_BUG_ON(!HAS_UC(i915));
 	GEM_BUG_ON(!wopcm->guc.size);
 	GEM_BUG_ON(!wopcm->guc.base);