| Message ID | 20190723120816.1361-2-philmd@redhat.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv/pmp: Convert to trace events | expand |
On Tue, Jul 23, 2019 at 5:08 AM Philippe Mathieu-Daudé <philmd@redhat.com> wrote: > > The RISC-V Physical Memory Protection is restricted to privileged > modes. Restrict its compilation to QEMU system builds. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/Makefile.objs | 3 ++- > target/riscv/pmp.c | 4 ---- > 2 files changed, 2 insertions(+), 5 deletions(-) > > diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs > index b1c79bc1d1..b754e4bf32 100644 > --- a/target/riscv/Makefile.objs > +++ b/target/riscv/Makefile.objs > @@ -1,4 +1,5 @@ > -obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o gdbstub.o pmp.o > +obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o gdbstub.o > +obj-$(CONFIG_SOFTMMU) += pmp.o > > DECODETREE = $(SRC_PATH)/scripts/decodetree.py > > diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c > index 958c7502a0..d836288cb4 100644 > --- a/target/riscv/pmp.c > +++ b/target/riscv/pmp.c > @@ -28,8 +28,6 @@ > #include "qapi/error.h" > #include "cpu.h" > > -#ifndef CONFIG_USER_ONLY > - > #define RISCV_DEBUG_PMP 0 > #define PMP_DEBUG(fmt, ...) \ > do { \ > @@ -382,5 +380,3 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index) > return 0; > } > } > - > -#endif > -- > 2.20.1 > >
diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index b1c79bc1d1..b754e4bf32 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -1,4 +1,5 @@ -obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o gdbstub.o pmp.o +obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o gdbstub.o +obj-$(CONFIG_SOFTMMU) += pmp.o DECODETREE = $(SRC_PATH)/scripts/decodetree.py diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 958c7502a0..d836288cb4 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -28,8 +28,6 @@ #include "qapi/error.h" #include "cpu.h" -#ifndef CONFIG_USER_ONLY - #define RISCV_DEBUG_PMP 0 #define PMP_DEBUG(fmt, ...) \ do { \ @@ -382,5 +380,3 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index) return 0; } } - -#endif
The RISC-V Physical Memory Protection is restricted to privileged modes. Restrict its compilation to QEMU system builds. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> --- target/riscv/Makefile.objs | 3 ++- target/riscv/pmp.c | 4 ---- 2 files changed, 2 insertions(+), 5 deletions(-)