| Message ID | 20190723134120.28441-1-colin.king@canonical.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [next] drm/amdgpu: remove redundant assignment to pointer 'ring' | expand |
On Tue, Jul 23, 2019 at 9:41 AM Colin King <colin.king@canonical.com> wrote: > > From: Colin Ian King <colin.king@canonical.com> > > The pointer 'ring' is being assigned a value that is never > read, hence the assignment is redundant and can be removed. > > Addresses-Coverity: ("Unused value") > Signed-off-by: Colin Ian King <colin.king@canonical.com> > --- > drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c > index 93b3500e522b..a2a8ca942f34 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c > @@ -1331,7 +1331,6 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, > WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, > UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); > > - ring = &adev->vcn.inst->ring_dec; > WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, > RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); > SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, While we don't use ring here, I think the assignment is useful to delineate that we are no longer working with the jpeg ring, but rather the decode ring. The mmUVD_RBC_RB_WPTR register is part of the decode ring, not jpeg. We would normally use the ring->wptr like we do for the other rings, but in this particular case, the value happens to be shadowed to a scratch register due to the way the dynamic power gating works on that ring. Alex > -- > 2.20.1 > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 93b3500e522b..a2a8ca942f34 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -1331,7 +1331,6 @@ static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); - ring = &adev->vcn.inst->ring_dec; WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,