| Message ID | 20190723213553.22300-8-julien.grall@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | xen/arm: Xen hardening for newer Armv8 | expand |
Julien Grall writes: > The definition of PRIregister varies between Arm32 and Arm64 (32-bit vs > 64-bit). However, some of the users uses the wrong padding. type: "users use" > For more consistency, the padding is now moved into the PRIregister and > varies depending on the architecture. I'm not sure this is the right thing to do. There are lots of code (especially in vgic) that does not use padding at all. Now it will print padding, even if original author does not wanted to. And, honestly it is hard to parse 15-16 zeroes in a row. I am suggesting to add another macro like PRIregister_pad or something like that. > Signed-off-by: Julien Grall <julien.grall@arm.com> > --- > xen/arch/arm/traps.c | 10 +++++----- > xen/include/asm-arm/types.h | 4 ++-- > 2 files changed, 7 insertions(+), 7 deletions(-) > > diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c > index ef37ca6bde..f062ae6f6a 100644 > --- a/xen/arch/arm/traps.c > +++ b/xen/arch/arm/traps.c > @@ -797,7 +797,7 @@ static void show_registers_32(const struct cpu_user_regs *regs, > > if ( guest_mode ) > { > - printk("USR: SP: %08"PRIx32" LR: %08"PRIregister"\n", > + printk("USR: SP: %08"PRIx32" LR: %"PRIregister"\n", > regs->sp_usr, regs->lr); > printk("SVC: SP: %08"PRIx32" LR: %08"PRIx32" SPSR:%08"PRIx32"\n", > regs->sp_svc, regs->lr_svc, regs->spsr_svc); > @@ -815,7 +815,7 @@ static void show_registers_32(const struct cpu_user_regs *regs, > #ifndef CONFIG_ARM_64 > else > { > - printk("HYP: SP: %08"PRIx32" LR: %08"PRIregister"\n", regs->sp, regs->lr); > + printk("HYP: SP: %08"PRIx32" LR: %"PRIregister"\n", regs->sp, regs->lr); > } > #endif > printk("\n"); > @@ -823,7 +823,7 @@ static void show_registers_32(const struct cpu_user_regs *regs, > if ( guest_mode ) > { > printk(" SCTLR: %"PRIregister"\n", ctxt->sctlr_el1); > - printk(" TCR: %08"PRIregister"\n", ctxt->tcr_el1); > + printk(" TCR: %"PRIregister"\n", ctxt->tcr_el1); > printk(" TTBR0: %016"PRIx64"\n", ctxt->ttbr0_el1); > printk(" TTBR1: %016"PRIx64"\n", ctxt->ttbr1_el1); > printk(" IFAR: %08"PRIx32", IFSR: %08"PRIx32"\n" > @@ -895,7 +895,7 @@ static void show_registers_64(const struct cpu_user_regs *regs, > printk(" FAR_EL1: %016"PRIx64"\n", ctxt->far); > printk("\n"); > printk(" SCTLR_EL1: %"PRIregister"\n", ctxt->sctlr_el1); > - printk(" TCR_EL1: %08"PRIregister"\n", ctxt->tcr_el1); > + printk(" TCR_EL1: %"PRIregister"\n", ctxt->tcr_el1); > printk(" TTBR0_EL1: %016"PRIx64"\n", ctxt->ttbr0_el1); > printk(" TTBR1_EL1: %016"PRIx64"\n", ctxt->ttbr1_el1); > printk("\n"); > @@ -934,7 +934,7 @@ static void _show_registers(const struct cpu_user_regs *regs, > printk("\n"); > > printk(" SCTLR_EL2: %08"PRIx32"\n", READ_SYSREG32(SCTLR_EL2)); > - printk(" HCR_EL2: %016"PRIregister"\n", READ_SYSREG(HCR_EL2)); > + printk(" HCR_EL2: %"PRIregister"\n", READ_SYSREG(HCR_EL2)); > printk(" TTBR0_EL2: %016"PRIx64"\n", READ_SYSREG64(TTBR0_EL2)); > printk("\n"); > printk(" ESR_EL2: %08"PRIx32"\n", regs->hsr); > diff --git a/xen/include/asm-arm/types.h b/xen/include/asm-arm/types.h > index 30f95078cb..89aae25ffe 100644 > --- a/xen/include/asm-arm/types.h > +++ b/xen/include/asm-arm/types.h > @@ -41,7 +41,7 @@ typedef u64 paddr_t; > #define INVALID_PADDR (~0ULL) > #define PRIpaddr "016llx" > typedef u32 register_t; > -#define PRIregister "x" > +#define PRIregister "08x" > #elif defined (CONFIG_ARM_64) > typedef signed long s64; > typedef unsigned long u64; > @@ -51,7 +51,7 @@ typedef u64 paddr_t; > #define INVALID_PADDR (~0UL) > #define PRIpaddr "016lx" > typedef u64 register_t; > -#define PRIregister "lx" > +#define PRIregister "016lx" > #endif > > #if defined(__SIZE_TYPE__) -- Volodymyr Babchuk at EPAM
Hi, On 26/07/2019 13:47, Volodymyr Babchuk wrote: > > Julien Grall writes: > >> The definition of PRIregister varies between Arm32 and Arm64 (32-bit vs >> 64-bit). However, some of the users uses the wrong padding. > type: "users use" > >> For more consistency, the padding is now moved into the PRIregister and >> varies depending on the architecture. > I'm not sure this is the right thing to do. There are lots of code > (especially in vgic) that does not use padding at all. Now it will print > padding, even if original author does not wanted to. And, honestly it is > hard to parse 15-16 zeroes in a row. Well, I am usually starting to read from the right to left. So, for me, 15-16 zeroes are easy to ignore ;). > > I am suggesting to add another macro like PRIregister_pad or something > like that. No, we should print register the same way everywhere. I am clearly against providing two different formats here for the same type. Otherwise this will lead to endless debate on which one you will chose in the code. Looking at the vGIC, they are mostly print for debug. If you reach them then there are probably already something wrong happening. So I think we can leave the extra zeroes there. Cheers,
Julien Grall writes: > Hi, > > On 26/07/2019 13:47, Volodymyr Babchuk wrote: >> >> Julien Grall writes: >> >>> The definition of PRIregister varies between Arm32 and Arm64 (32-bit vs >>> 64-bit). However, some of the users uses the wrong padding. >> type: "users use" >> >>> For more consistency, the padding is now moved into the PRIregister and >>> varies depending on the architecture. >> I'm not sure this is the right thing to do. There are lots of code >> (especially in vgic) that does not use padding at all. Now it will print >> padding, even if original author does not wanted to. And, honestly it is >> hard to parse 15-16 zeroes in a row. > > Well, I am usually starting to read from the right to left. So, for > me, 15-16 zeroes are easy to ignore ;). And what if there only one bit set on position 31 or 35? :) Personally, I'd like to see such number grouped like "FEDCBA98 76543210" Anyways, this is matter of personal taste. I'm okay with padding. >> >> I am suggesting to add another macro like PRIregister_pad or something >> like that. > > No, we should print register the same way everywhere. I am clearly against > providing two different formats here for the same type. Otherwise this > will lead to endless debate on which one you will chose in the code. Okay then. But at least you should mention in the commit message, that this change will affect other prints, not only the ones in the diff.
On 26/07/2019 15:21, Volodymyr Babchuk wrote: > > Julien Grall writes: > >> Hi, >> >> On 26/07/2019 13:47, Volodymyr Babchuk wrote: >>> >>> Julien Grall writes: >>> >>>> The definition of PRIregister varies between Arm32 and Arm64 (32-bit vs >>>> 64-bit). However, some of the users uses the wrong padding. >>> type: "users use" >>> >>>> For more consistency, the padding is now moved into the PRIregister and >>>> varies depending on the architecture. >>> I'm not sure this is the right thing to do. There are lots of code >>> (especially in vgic) that does not use padding at all. Now it will print >>> padding, even if original author does not wanted to. And, honestly it is >>> hard to parse 15-16 zeroes in a row. >> >> Well, I am usually starting to read from the right to left. So, for >> me, 15-16 zeroes are easy to ignore ;). > And what if there only one bit set on position 31 or 35? :) That's why you have tools to help you figuring out the position of a bit... > Personally, I'd like to see such number grouped like "FEDCBA98 76543210" > Anyways, this is matter of personal taste. I'm okay with padding. Patch are welcomed ;). > >>> >>> I am suggesting to add another macro like PRIregister_pad or something >>> like that. >> >> No, we should print register the same way everywhere. I am clearly against >> providing two different formats here for the same type. Otherwise this >> will lead to endless debate on which one you will chose in the code. > Okay then. But at least you should mention in the commit message, that > this change will affect other prints, not only the ones in the diff. This was kind of implied with "consistency". But I am not going to argue here, there are more important stuff to focus. Cheers,
On 23/07/2019 22:35, Julien Grall wrote: > The definition of PRIregister varies between Arm32 and Arm64 (32-bit vs > 64-bit). However, some of the users uses the wrong padding. > > For more consistency, the padding is now moved into the PRIregister and > varies depending on the architecture. Below a suggested new commit message: "The definition of PRIregister varies between Arm32 and Arm64 (32-bit vs 64-bit). However, some of the users uses the wrong padding and others are not using padding at all. For more consistency, the padding is now moved into the PRIregister and varies depending on the architecture."
Julien Grall writes: > On 23/07/2019 22:35, Julien Grall wrote: >> The definition of PRIregister varies between Arm32 and Arm64 (32-bit vs >> 64-bit). However, some of the users uses the wrong padding. >> >> For more consistency, the padding is now moved into the PRIregister and >> varies depending on the architecture. > > Below a suggested new commit message: > > "The definition of PRIregister varies between Arm32 and Arm64 (32-bit vs > 64-bit). However, some of the users uses the wrong padding and others are > not using padding at all. > > For more consistency, the padding is now moved into the PRIregister and > varies depending on the architecture." With this commit message: Reviewed-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
On Fri, 26 Jul 2019, Volodymyr Babchuk wrote: > > On 23/07/2019 22:35, Julien Grall wrote: > >> The definition of PRIregister varies between Arm32 and Arm64 (32-bit vs > >> 64-bit). However, some of the users uses the wrong padding. > >> > >> For more consistency, the padding is now moved into the PRIregister and > >> varies depending on the architecture. > > > > Below a suggested new commit message: > > > > "The definition of PRIregister varies between Arm32 and Arm64 (32-bit vs > > 64-bit). However, some of the users uses the wrong padding and others are > > not using padding at all. > > > > For more consistency, the padding is now moved into the PRIregister and > > varies depending on the architecture." > With this commit message: > > Reviewed-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Acked-by: Stefano Stabellini <sstabellini@kernel.org>
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c index ef37ca6bde..f062ae6f6a 100644 --- a/xen/arch/arm/traps.c +++ b/xen/arch/arm/traps.c @@ -797,7 +797,7 @@ static void show_registers_32(const struct cpu_user_regs *regs, if ( guest_mode ) { - printk("USR: SP: %08"PRIx32" LR: %08"PRIregister"\n", + printk("USR: SP: %08"PRIx32" LR: %"PRIregister"\n", regs->sp_usr, regs->lr); printk("SVC: SP: %08"PRIx32" LR: %08"PRIx32" SPSR:%08"PRIx32"\n", regs->sp_svc, regs->lr_svc, regs->spsr_svc); @@ -815,7 +815,7 @@ static void show_registers_32(const struct cpu_user_regs *regs, #ifndef CONFIG_ARM_64 else { - printk("HYP: SP: %08"PRIx32" LR: %08"PRIregister"\n", regs->sp, regs->lr); + printk("HYP: SP: %08"PRIx32" LR: %"PRIregister"\n", regs->sp, regs->lr); } #endif printk("\n"); @@ -823,7 +823,7 @@ static void show_registers_32(const struct cpu_user_regs *regs, if ( guest_mode ) { printk(" SCTLR: %"PRIregister"\n", ctxt->sctlr_el1); - printk(" TCR: %08"PRIregister"\n", ctxt->tcr_el1); + printk(" TCR: %"PRIregister"\n", ctxt->tcr_el1); printk(" TTBR0: %016"PRIx64"\n", ctxt->ttbr0_el1); printk(" TTBR1: %016"PRIx64"\n", ctxt->ttbr1_el1); printk(" IFAR: %08"PRIx32", IFSR: %08"PRIx32"\n" @@ -895,7 +895,7 @@ static void show_registers_64(const struct cpu_user_regs *regs, printk(" FAR_EL1: %016"PRIx64"\n", ctxt->far); printk("\n"); printk(" SCTLR_EL1: %"PRIregister"\n", ctxt->sctlr_el1); - printk(" TCR_EL1: %08"PRIregister"\n", ctxt->tcr_el1); + printk(" TCR_EL1: %"PRIregister"\n", ctxt->tcr_el1); printk(" TTBR0_EL1: %016"PRIx64"\n", ctxt->ttbr0_el1); printk(" TTBR1_EL1: %016"PRIx64"\n", ctxt->ttbr1_el1); printk("\n"); @@ -934,7 +934,7 @@ static void _show_registers(const struct cpu_user_regs *regs, printk("\n"); printk(" SCTLR_EL2: %08"PRIx32"\n", READ_SYSREG32(SCTLR_EL2)); - printk(" HCR_EL2: %016"PRIregister"\n", READ_SYSREG(HCR_EL2)); + printk(" HCR_EL2: %"PRIregister"\n", READ_SYSREG(HCR_EL2)); printk(" TTBR0_EL2: %016"PRIx64"\n", READ_SYSREG64(TTBR0_EL2)); printk("\n"); printk(" ESR_EL2: %08"PRIx32"\n", regs->hsr); diff --git a/xen/include/asm-arm/types.h b/xen/include/asm-arm/types.h index 30f95078cb..89aae25ffe 100644 --- a/xen/include/asm-arm/types.h +++ b/xen/include/asm-arm/types.h @@ -41,7 +41,7 @@ typedef u64 paddr_t; #define INVALID_PADDR (~0ULL) #define PRIpaddr "016llx" typedef u32 register_t; -#define PRIregister "x" +#define PRIregister "08x" #elif defined (CONFIG_ARM_64) typedef signed long s64; typedef unsigned long u64; @@ -51,7 +51,7 @@ typedef u64 paddr_t; #define INVALID_PADDR (~0UL) #define PRIpaddr "016lx" typedef u64 register_t; -#define PRIregister "lx" +#define PRIregister "016lx" #endif #if defined(__SIZE_TYPE__)
The definition of PRIregister varies between Arm32 and Arm64 (32-bit vs 64-bit). However, some of the users uses the wrong padding. For more consistency, the padding is now moved into the PRIregister and varies depending on the architecture. Signed-off-by: Julien Grall <julien.grall@arm.com> --- xen/arch/arm/traps.c | 10 +++++----- xen/include/asm-arm/types.h | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-)