| Message ID | 20190730144147.3694-1-will@kernel.org (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 332e5281a4e8269b96233a7babc98b03596b7e6d |
| Headers | show |
| Series | arm64: esr: Add ESR exception class encoding for trapped ERET | expand |
On Tue, Jul 30, 2019 at 03:41:47PM +0100, Will Deacon wrote: > The ESR.EC encoding of 0b011010 (0x1a) describes an exception generated > by an ERET, ERETAA or ERETAB instruction as a result of a nested > virtualisation trap to EL2. > > Add an encoding for this EC and a string description so that we identify > it correctly if we take one unexpectedly. > > Signed-off-by: Will Deacon <will@kernel.org> Acked-by: Mark Rutland <mark.rutland@arm.com> Mark. > --- > arch/arm64/include/asm/esr.h | 3 ++- > arch/arm64/kernel/traps.c | 1 + > 2 files changed, 3 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h > index 65ac18400979..cb29253ae86b 100644 > --- a/arch/arm64/include/asm/esr.h > +++ b/arch/arm64/include/asm/esr.h > @@ -34,7 +34,8 @@ > #define ESR_ELx_EC_SMC64 (0x17) /* EL2 and above */ > #define ESR_ELx_EC_SYS64 (0x18) > #define ESR_ELx_EC_SVE (0x19) > -/* Unallocated EC: 0x1A - 0x1E */ > +#define ESR_ELx_EC_ERET (0x1a) /* EL2 only */ > +/* Unallocated EC: 0x1b - 0x1E */ > #define ESR_ELx_EC_IMP_DEF (0x1f) /* EL3 only */ > #define ESR_ELx_EC_IABT_LOW (0x20) > #define ESR_ELx_EC_IABT_CUR (0x21) > diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c > index d3313797cca9..42c8422cdf4a 100644 > --- a/arch/arm64/kernel/traps.c > +++ b/arch/arm64/kernel/traps.c > @@ -743,6 +743,7 @@ static const char *esr_class_str[] = { > [ESR_ELx_EC_SMC64] = "SMC (AArch64)", > [ESR_ELx_EC_SYS64] = "MSR/MRS (AArch64)", > [ESR_ELx_EC_SVE] = "SVE", > + [ESR_ELx_EC_ERET] = "ERET/ERETAA/ERETAB", > [ESR_ELx_EC_IMP_DEF] = "EL3 IMP DEF", > [ESR_ELx_EC_IABT_LOW] = "IABT (lower EL)", > [ESR_ELx_EC_IABT_CUR] = "IABT (current EL)", > -- > 2.11.0 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On 30/07/2019 15:41, Will Deacon wrote: > The ESR.EC encoding of 0b011010 (0x1a) describes an exception generated > by an ERET, ERETAA or ERETAB instruction as a result of a nested > virtualisation trap to EL2. > > Add an encoding for this EC and a string description so that we identify > it correctly if we take one unexpectedly. > > Signed-off-by: Will Deacon <will@kernel.org> Acked-by: Marc Zyngier <maz@kernel.org> M.
diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h index 65ac18400979..cb29253ae86b 100644 --- a/arch/arm64/include/asm/esr.h +++ b/arch/arm64/include/asm/esr.h @@ -34,7 +34,8 @@ #define ESR_ELx_EC_SMC64 (0x17) /* EL2 and above */ #define ESR_ELx_EC_SYS64 (0x18) #define ESR_ELx_EC_SVE (0x19) -/* Unallocated EC: 0x1A - 0x1E */ +#define ESR_ELx_EC_ERET (0x1a) /* EL2 only */ +/* Unallocated EC: 0x1b - 0x1E */ #define ESR_ELx_EC_IMP_DEF (0x1f) /* EL3 only */ #define ESR_ELx_EC_IABT_LOW (0x20) #define ESR_ELx_EC_IABT_CUR (0x21) diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c index d3313797cca9..42c8422cdf4a 100644 --- a/arch/arm64/kernel/traps.c +++ b/arch/arm64/kernel/traps.c @@ -743,6 +743,7 @@ static const char *esr_class_str[] = { [ESR_ELx_EC_SMC64] = "SMC (AArch64)", [ESR_ELx_EC_SYS64] = "MSR/MRS (AArch64)", [ESR_ELx_EC_SVE] = "SVE", + [ESR_ELx_EC_ERET] = "ERET/ERETAA/ERETAB", [ESR_ELx_EC_IMP_DEF] = "EL3 IMP DEF", [ESR_ELx_EC_IABT_LOW] = "IABT (lower EL)", [ESR_ELx_EC_IABT_CUR] = "IABT (current EL)",
The ESR.EC encoding of 0b011010 (0x1a) describes an exception generated by an ERET, ERETAA or ERETAB instruction as a result of a nested virtualisation trap to EL2. Add an encoding for this EC and a string description so that we identify it correctly if we take one unexpectedly. Signed-off-by: Will Deacon <will@kernel.org> --- arch/arm64/include/asm/esr.h | 3 ++- arch/arm64/kernel/traps.c | 1 + 2 files changed, 3 insertions(+), 1 deletion(-)