[v3,14/19] dt-bindings: pci: add PHY properties to Armada 7K/8K controller bindings
diff mbox series

Message ID 20190731122126.3049-15-miquel.raynal@bootlin.com
State New
Headers show
Series
  • Enhance CP110 COMPHY support
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Commit Message

Miquel Raynal July 31, 2019, 12:21 p.m. UTC
Armada CP110 PCIe controller can have from one to four PHYs for
configuring SERDES lanes (PCIe x1, PCIe x2 or PCIe x4). Describe the
phys and phy-names properties in the bindings.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
 Documentation/devicetree/bindings/pci/pci-armada8k.txt | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

Rob Herring Aug. 21, 2019, 6:28 p.m. UTC | #1
On Wed, Jul 31, 2019 at 02:21:21PM +0200, Miquel Raynal wrote:
> Armada CP110 PCIe controller can have from one to four PHYs for
> configuring SERDES lanes (PCIe x1, PCIe x2 or PCIe x4). Describe the
> phys and phy-names properties in the bindings.
> 
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
>  Documentation/devicetree/bindings/pci/pci-armada8k.txt | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
> index 9e3fc15e1af8..7cf12162aa4e 100644
> --- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt
> +++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
> @@ -17,6 +17,12 @@ Required properties:
>     name must be "core" for the first clock and "reg" for the second
>     one
>  
> +Optional properties:
> +- phys: phandle(s) to PHY node(s) following the generic PHY bindings.
> +	Either 1, 2 or 4 PHYs might be needed depending on the number of
> +	PCIe lanes.
> +- phy-names: names of the PHYs.

You need to enumerate what the names are. Based on your example in v2, I 
don't think the names are really valuable unless you can skip lanes.

Rob
Miquel Raynal Aug. 24, 2019, 10:15 a.m. UTC | #2
Hi Rob,

Rob Herring <robh@kernel.org> wrote on Wed, 21 Aug 2019 13:28:57 -0500:

> On Wed, Jul 31, 2019 at 02:21:21PM +0200, Miquel Raynal wrote:
> > Armada CP110 PCIe controller can have from one to four PHYs for
> > configuring SERDES lanes (PCIe x1, PCIe x2 or PCIe x4). Describe the
> > phys and phy-names properties in the bindings.
> > 
> > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> > ---
> >  Documentation/devicetree/bindings/pci/pci-armada8k.txt | 6 ++++++
> >  1 file changed, 6 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
> > index 9e3fc15e1af8..7cf12162aa4e 100644
> > --- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt
> > +++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
> > @@ -17,6 +17,12 @@ Required properties:
> >     name must be "core" for the first clock and "reg" for the second
> >     one
> >  
> > +Optional properties:
> > +- phys: phandle(s) to PHY node(s) following the generic PHY bindings.
> > +	Either 1, 2 or 4 PHYs might be needed depending on the number of
> > +	PCIe lanes.
> > +- phy-names: names of the PHYs.  
> 
> You need to enumerate what the names are. Based on your example in v2, I 
> don't think the names are really valuable unless you can skip lanes.

I don't know any setup doing it but yes, I suppose you could skip lanes.

Kishon asked me to rebase on phy-next, I'll enumerate the names when
resending.

Thanks,
Miquèl

Patch
diff mbox series

diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
index 9e3fc15e1af8..7cf12162aa4e 100644
--- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt
+++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
@@ -17,6 +17,12 @@  Required properties:
    name must be "core" for the first clock and "reg" for the second
    one
 
+Optional properties:
+- phys: phandle(s) to PHY node(s) following the generic PHY bindings.
+	Either 1, 2 or 4 PHYs might be needed depending on the number of
+	PCIe lanes.
+- phy-names: names of the PHYs.
+
 Example:
 
 	pcie@f2600000 {