| Message ID | 1564607463-28802-11-git-send-email-skomatineni@nvidia.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | SC7 entry and exit support for Tegra210 | expand |
01.08.2019 0:10, Sowjanya Komatineni пишет: > This patch implements DFLL suspend and resume operation. > > During system suspend entry, CPU clock will switch CPU to safe > clock source of PLLP and disables DFLL clock output. > > DFLL driver suspend confirms DFLL disable state and errors out on > being active. > > DFLL is re-initialized during the DFLL driver resume as it goes > through complete reset during suspend entry. > > Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> > --- > drivers/clk/tegra/clk-dfll.c | 56 ++++++++++++++++++++++++++++++ > drivers/clk/tegra/clk-dfll.h | 2 ++ > drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 1 + > 3 files changed, 59 insertions(+) > > diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c > index f8688c2ddf1a..9900097ec2aa 100644 > --- a/drivers/clk/tegra/clk-dfll.c > +++ b/drivers/clk/tegra/clk-dfll.c > @@ -1513,6 +1513,62 @@ static int dfll_init(struct tegra_dfll *td) > return ret; > } > > +/** > + * tegra_dfll_suspend - check DFLL is disabled > + * @dev: DFLL device * > + * > + * DFLL clock should be disabled by the CPUFreq driver. So, make > + * sure it is disabled and disable all clocks needed by the DFLL. > + */ > +int tegra_dfll_suspend(struct device *dev) > +{ > + struct tegra_dfll *td = dev_get_drvdata(dev); > + > + if (dfll_is_running(td)) { > + dev_err(td->dev, "dfll is enabled while shouldn't be\n"); > + return -EBUSY; > + } > + > + reset_control_assert(td->dvco_rst); > + > + return 0; > +} > +EXPORT_SYMBOL(tegra_dfll_suspend); > + > +/** > + * tegra_dfll_resume - reinitialize DFLL on resume > + * @dev: DFLL instance > + * > + * DFLL is disabled and reset during suspend and resume. > + * So, reinitialize the DFLL IP block back for use. > + * DFLL clock is enabled later in closed loop mode by CPUFreq > + * driver before switching its clock source to DFLL output. > + */ > +int tegra_dfll_resume(struct device *dev) > +{ > + struct tegra_dfll *td = dev_get_drvdata(dev); > + > + reset_control_deassert(td->dvco_rst); > + > + pm_runtime_irq_safe(td->dev); Please see my previous reply.
01.08.2019 13:18, Dmitry Osipenko пишет: > 01.08.2019 0:10, Sowjanya Komatineni пишет: >> This patch implements DFLL suspend and resume operation. >> >> During system suspend entry, CPU clock will switch CPU to safe >> clock source of PLLP and disables DFLL clock output. >> >> DFLL driver suspend confirms DFLL disable state and errors out on >> being active. >> >> DFLL is re-initialized during the DFLL driver resume as it goes >> through complete reset during suspend entry. >> >> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> >> --- >> drivers/clk/tegra/clk-dfll.c | 56 ++++++++++++++++++++++++++++++ >> drivers/clk/tegra/clk-dfll.h | 2 ++ >> drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 1 + >> 3 files changed, 59 insertions(+) >> >> diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c >> index f8688c2ddf1a..9900097ec2aa 100644 >> --- a/drivers/clk/tegra/clk-dfll.c >> +++ b/drivers/clk/tegra/clk-dfll.c >> @@ -1513,6 +1513,62 @@ static int dfll_init(struct tegra_dfll *td) >> return ret; >> } >> >> +/** >> + * tegra_dfll_suspend - check DFLL is disabled >> + * @dev: DFLL device * >> + * >> + * DFLL clock should be disabled by the CPUFreq driver. So, make >> + * sure it is disabled and disable all clocks needed by the DFLL. >> + */ >> +int tegra_dfll_suspend(struct device *dev) >> +{ >> + struct tegra_dfll *td = dev_get_drvdata(dev); >> + >> + if (dfll_is_running(td)) { >> + dev_err(td->dev, "dfll is enabled while shouldn't be\n"); >> + return -EBUSY; >> + } >> + >> + reset_control_assert(td->dvco_rst); >> + >> + return 0; >> +} >> +EXPORT_SYMBOL(tegra_dfll_suspend); >> + >> +/** >> + * tegra_dfll_resume - reinitialize DFLL on resume >> + * @dev: DFLL instance >> + * >> + * DFLL is disabled and reset during suspend and resume. >> + * So, reinitialize the DFLL IP block back for use. >> + * DFLL clock is enabled later in closed loop mode by CPUFreq >> + * driver before switching its clock source to DFLL output. >> + */ >> +int tegra_dfll_resume(struct device *dev) >> +{ >> + struct tegra_dfll *td = dev_get_drvdata(dev); >> + >> + reset_control_deassert(td->dvco_rst); >> + >> + pm_runtime_irq_safe(td->dev); > > Please see my previous reply. > Also, you should always bump version of the patches no matter what. otherwise it turns out very confusing.
01.08.2019 19:10, Sowjanya Komatineni пишет: > I didn’t updated any patches. This is still same v7 just resent with > CPUFreq maintainers in CC as I missed to add them earlier. There are now two different threads for the same patches, which is not very good. When I said that CPUFreq maintainers should be CC'ed, I didn't mean to resend it all, sorry for not being clear about it. You should've wait for more comments to the original patches and then make a v8. I suggest to do the same in the current situation as well, please address all the current comments and wait for 1-2 days, then make a v8.
On 8/1/19 10:10 AM, Dmitry Osipenko wrote: > 01.08.2019 19:10, Sowjanya Komatineni пишет: >> I didn’t updated any patches. This is still same v7 just resent with >> CPUFreq maintainers in CC as I missed to add them earlier. > There are now two different threads for the same patches, which is not > very good. When I said that CPUFreq maintainers should be CC'ed, I > didn't mean to resend it all, sorry for not being clear about it. You > should've wait for more comments to the original patches and then make a > v8. I suggest to do the same in the current situation as well, please > address all the current comments and wait for 1-2 days, then make a v8. Thought version bump is only when changes were made. Got it now. Thanks Dmitry. Sure, will give some time for all feedbacks before sending V8.
diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c index f8688c2ddf1a..9900097ec2aa 100644 --- a/drivers/clk/tegra/clk-dfll.c +++ b/drivers/clk/tegra/clk-dfll.c @@ -1513,6 +1513,62 @@ static int dfll_init(struct tegra_dfll *td) return ret; } +/** + * tegra_dfll_suspend - check DFLL is disabled + * @dev: DFLL device * + * + * DFLL clock should be disabled by the CPUFreq driver. So, make + * sure it is disabled and disable all clocks needed by the DFLL. + */ +int tegra_dfll_suspend(struct device *dev) +{ + struct tegra_dfll *td = dev_get_drvdata(dev); + + if (dfll_is_running(td)) { + dev_err(td->dev, "dfll is enabled while shouldn't be\n"); + return -EBUSY; + } + + reset_control_assert(td->dvco_rst); + + return 0; +} +EXPORT_SYMBOL(tegra_dfll_suspend); + +/** + * tegra_dfll_resume - reinitialize DFLL on resume + * @dev: DFLL instance + * + * DFLL is disabled and reset during suspend and resume. + * So, reinitialize the DFLL IP block back for use. + * DFLL clock is enabled later in closed loop mode by CPUFreq + * driver before switching its clock source to DFLL output. + */ +int tegra_dfll_resume(struct device *dev) +{ + struct tegra_dfll *td = dev_get_drvdata(dev); + + reset_control_deassert(td->dvco_rst); + + pm_runtime_irq_safe(td->dev); + pm_runtime_get_sync(td->dev); + + dfll_set_mode(td, DFLL_DISABLED); + dfll_set_default_params(td); + + if (td->soc->init_clock_trimmers) + td->soc->init_clock_trimmers(); + + dfll_set_open_loop_config(td); + + dfll_init_out_if(td); + + pm_runtime_put_sync(td->dev); + + return 0; +} +EXPORT_SYMBOL(tegra_dfll_resume); + /* * DT data fetch */ diff --git a/drivers/clk/tegra/clk-dfll.h b/drivers/clk/tegra/clk-dfll.h index 1b14ebe7268b..fb209eb5f365 100644 --- a/drivers/clk/tegra/clk-dfll.h +++ b/drivers/clk/tegra/clk-dfll.h @@ -42,5 +42,7 @@ int tegra_dfll_register(struct platform_device *pdev, struct tegra_dfll_soc_data *tegra_dfll_unregister(struct platform_device *pdev); int tegra_dfll_runtime_suspend(struct device *dev); int tegra_dfll_runtime_resume(struct device *dev); +int tegra_dfll_suspend(struct device *dev); +int tegra_dfll_resume(struct device *dev); #endif /* __DRIVERS_CLK_TEGRA_CLK_DFLL_H */ diff --git a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c index e84b6d52cbbd..2ac2679d696d 100644 --- a/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c +++ b/drivers/clk/tegra/clk-tegra124-dfll-fcpu.c @@ -631,6 +631,7 @@ static int tegra124_dfll_fcpu_remove(struct platform_device *pdev) static const struct dev_pm_ops tegra124_dfll_pm_ops = { SET_RUNTIME_PM_OPS(tegra_dfll_runtime_suspend, tegra_dfll_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(tegra_dfll_suspend, tegra_dfll_resume) }; static struct platform_driver tegra124_dfll_fcpu_driver = {
This patch implements DFLL suspend and resume operation. During system suspend entry, CPU clock will switch CPU to safe clock source of PLLP and disables DFLL clock output. DFLL driver suspend confirms DFLL disable state and errors out on being active. DFLL is re-initialized during the DFLL driver resume as it goes through complete reset during suspend entry. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> --- drivers/clk/tegra/clk-dfll.c | 56 ++++++++++++++++++++++++++++++ drivers/clk/tegra/clk-dfll.h | 2 ++ drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 1 + 3 files changed, 59 insertions(+)