| Message ID | 20190805085847.25554-4-linus.walleij@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | PL111 DRM conversion of nspire | expand |
Hi Linus, On Mon, Aug 05, 2019 at 10:58:46AM +0200, Linus Walleij wrote: > This adds support for the TI nspire panels to the simple panel > roster. This code is based on arch/arm/mach-nspire/clcd.c. > This includes likely the first grayscale panel supported. > > These panels will be used with the PL11x DRM driver. > > Cc: Daniel Tang <dt.tangr@gmail.com> > Cc: Fabian Vogt <fabian@ritter-vogt.de> > Tested-by: Fabian Vogt <fabian@ritter-vogt.de> > Signed-off-by: Linus Walleij <linus.walleij@linaro.org> You can now add my: Reviewed-by: Sam Ravnborg <sam@ravnborg.org> I assume this will be applied as one series and you will do it when ready. Sam > --- > ChangeLog v1->v2: > - Bump clock frequency to 10 MHz after Fabian's trial-and-error > - Changed vsymbol names to ti_nspire_* > - Sorted alphabetically > - Specify positive edge on the classic display bus > --- > drivers/gpu/drm/panel/panel-simple.c | 64 ++++++++++++++++++++++++++++ > 1 file changed, 64 insertions(+) > > diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c > index 5a93c4edf1e4..96f894b44313 100644 > --- a/drivers/gpu/drm/panel/panel-simple.c > +++ b/drivers/gpu/drm/panel/panel-simple.c > @@ -2578,6 +2578,64 @@ static const struct panel_desc tianma_tm070rvhg71 = { > .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, > }; > > +static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { > + { > + .clock = 10000, > + .hdisplay = 320, > + .hsync_start = 320 + 50, > + .hsync_end = 320 + 50 + 6, > + .htotal = 320 + 50 + 6 + 38, > + .vdisplay = 240, > + .vsync_start = 240 + 3, > + .vsync_end = 240 + 3 + 1, > + .vtotal = 240 + 3 + 1 + 17, > + .vrefresh = 60, > + .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, > + }, > +}; > + > +static const struct panel_desc ti_nspire_cx_lcd_panel = { > + .modes = ti_nspire_cx_lcd_mode, > + .num_modes = 1, > + .bpc = 8, > + .size = { > + .width = 65, > + .height = 49, > + }, > + .bus_format = MEDIA_BUS_FMT_RGB888_1X24, > + .bus_flags = DRM_BUS_FLAG_PIXDATA_NEGEDGE, > +}; > + > +static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { > + { > + .clock = 10000, > + .hdisplay = 320, > + .hsync_start = 320 + 6, > + .hsync_end = 320 + 6 + 6, > + .htotal = 320 + 6 + 6 + 6, > + .vdisplay = 240, > + .vsync_start = 240 + 0, > + .vsync_end = 240 + 0 + 1, > + .vtotal = 240 + 0 + 1 + 0, > + .vrefresh = 60, > + .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, > + }, > +}; > + > +static const struct panel_desc ti_nspire_classic_lcd_panel = { > + .modes = ti_nspire_classic_lcd_mode, > + .num_modes = 1, > + /* The grayscale panel has 8 bit for the color .. Y (black) */ > + .bpc = 8, > + .size = { > + .width = 71, > + .height = 53, > + }, > + /* This is the grayscale bus format */ > + .bus_format = MEDIA_BUS_FMT_Y8_1X8, > + .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE, > +}; > + > static const struct drm_display_mode toshiba_lt089ac29000_mode = { > .clock = 79500, > .hdisplay = 1280, > @@ -3029,6 +3087,12 @@ static const struct of_device_id platform_of_match[] = { > }, { > .compatible = "tianma,tm070rvhg71", > .data = &tianma_tm070rvhg71, > + }, { > + .compatible = "ti,nspire-cx-lcd-panel", > + .data = &ti_nspire_cx_lcd_panel, > + }, { > + .compatible = "ti,nspire-classic-lcd-panel", > + .data = &ti_nspire_classic_lcd_panel, > }, { > .compatible = "toshiba,lt089ac29000", > .data = &toshiba_lt089ac29000, > -- > 2.21.0 > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 5a93c4edf1e4..96f894b44313 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -2578,6 +2578,64 @@ static const struct panel_desc tianma_tm070rvhg71 = { .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, }; +static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = { + { + .clock = 10000, + .hdisplay = 320, + .hsync_start = 320 + 50, + .hsync_end = 320 + 50 + 6, + .htotal = 320 + 50 + 6 + 38, + .vdisplay = 240, + .vsync_start = 240 + 3, + .vsync_end = 240 + 3 + 1, + .vtotal = 240 + 3 + 1 + 17, + .vrefresh = 60, + .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, + }, +}; + +static const struct panel_desc ti_nspire_cx_lcd_panel = { + .modes = ti_nspire_cx_lcd_mode, + .num_modes = 1, + .bpc = 8, + .size = { + .width = 65, + .height = 49, + }, + .bus_format = MEDIA_BUS_FMT_RGB888_1X24, + .bus_flags = DRM_BUS_FLAG_PIXDATA_NEGEDGE, +}; + +static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = { + { + .clock = 10000, + .hdisplay = 320, + .hsync_start = 320 + 6, + .hsync_end = 320 + 6 + 6, + .htotal = 320 + 6 + 6 + 6, + .vdisplay = 240, + .vsync_start = 240 + 0, + .vsync_end = 240 + 0 + 1, + .vtotal = 240 + 0 + 1 + 0, + .vrefresh = 60, + .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC, + }, +}; + +static const struct panel_desc ti_nspire_classic_lcd_panel = { + .modes = ti_nspire_classic_lcd_mode, + .num_modes = 1, + /* The grayscale panel has 8 bit for the color .. Y (black) */ + .bpc = 8, + .size = { + .width = 71, + .height = 53, + }, + /* This is the grayscale bus format */ + .bus_format = MEDIA_BUS_FMT_Y8_1X8, + .bus_flags = DRM_BUS_FLAG_PIXDATA_POSEDGE, +}; + static const struct drm_display_mode toshiba_lt089ac29000_mode = { .clock = 79500, .hdisplay = 1280, @@ -3029,6 +3087,12 @@ static const struct of_device_id platform_of_match[] = { }, { .compatible = "tianma,tm070rvhg71", .data = &tianma_tm070rvhg71, + }, { + .compatible = "ti,nspire-cx-lcd-panel", + .data = &ti_nspire_cx_lcd_panel, + }, { + .compatible = "ti,nspire-classic-lcd-panel", + .data = &ti_nspire_classic_lcd_panel, }, { .compatible = "toshiba,lt089ac29000", .data = &toshiba_lt089ac29000,