| Message ID | 20190805130952.4415-2-peter.maydell@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/arm: Fix routing of singlestep exceptions | expand |
On 8/5/19 3:09 PM, Peter Maydell wrote: > Factor out code to 'generate a singlestep exception', which is > currently repeated in four places. > > To do this we need to also pull the identical copies of the > gen-exception() function out of translate-a64.c and translate.c > into translate.h. > > (There is a bug in the code: we're taking the exception to the wrong > target EL. This will be simpler to fix if there's only one place to > do it.) > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> > --- > target/arm/translate.h | 23 +++++++++++++++++++++++ > target/arm/translate-a64.c | 19 ++----------------- > target/arm/translate.c | 20 ++------------------ > 3 files changed, 27 insertions(+), 35 deletions(-) > > diff --git a/target/arm/translate.h b/target/arm/translate.h > index a20f6e20568..45053190baa 100644 > --- a/target/arm/translate.h > +++ b/target/arm/translate.h > @@ -2,6 +2,7 @@ > #define TARGET_ARM_TRANSLATE_H > > #include "exec/translator.h" > +#include "internals.h" > > > /* internal defines */ > @@ -232,6 +233,28 @@ static inline void gen_ss_advance(DisasContext *s) > } > } > > +static inline void gen_exception(int excp, uint32_t syndrome, > + uint32_t target_el) > +{ > + TCGv_i32 tcg_excp = tcg_const_i32(excp); > + TCGv_i32 tcg_syn = tcg_const_i32(syndrome); > + TCGv_i32 tcg_el = tcg_const_i32(target_el); > + > + gen_helper_exception_with_syndrome(cpu_env, tcg_excp, > + tcg_syn, tcg_el); > + > + tcg_temp_free_i32(tcg_el); > + tcg_temp_free_i32(tcg_syn); > + tcg_temp_free_i32(tcg_excp); > +} > + > +/* Generate an architectural singlestep exception */ > +static inline void gen_swstep_exception(DisasContext *s, int isv, int ex) > +{ > + gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, isv, ex), > + default_exception_el(s)); > +} > + > /* > * Given a VFP floating point constant encoded into an 8 bit immediate in an > * instruction, expand it to the actual constant value of the specified > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index d3231477a27..f6729b96fd0 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -253,19 +253,6 @@ static void gen_exception_internal(int excp) > tcg_temp_free_i32(tcg_excp); > } > > -static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el) > -{ > - TCGv_i32 tcg_excp = tcg_const_i32(excp); > - TCGv_i32 tcg_syn = tcg_const_i32(syndrome); > - TCGv_i32 tcg_el = tcg_const_i32(target_el); > - > - gen_helper_exception_with_syndrome(cpu_env, tcg_excp, > - tcg_syn, tcg_el); > - tcg_temp_free_i32(tcg_el); > - tcg_temp_free_i32(tcg_syn); > - tcg_temp_free_i32(tcg_excp); > -} > - > static void gen_exception_internal_insn(DisasContext *s, int offset, int excp) > { > gen_a64_set_pc_im(s->pc - offset); > @@ -305,8 +292,7 @@ static void gen_step_complete_exception(DisasContext *s) > * of the exception, and our syndrome information is always correct. > */ > gen_ss_advance(s); > - gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), > - default_exception_el(s)); > + gen_swstep_exception(s, 1, s->is_ldex); > s->base.is_jmp = DISAS_NORETURN; > } > > @@ -14261,8 +14247,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) > * bits should be zero. > */ > assert(dc->base.num_insns == 1); > - gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), > - default_exception_el(dc)); > + gen_swstep_exception(dc, 0, 0); > dc->base.is_jmp = DISAS_NORETURN; > } else { > disas_a64_insn(env, dc); > diff --git a/target/arm/translate.c b/target/arm/translate.c > index 7853462b21b..19b9d8f2725 100644 > --- a/target/arm/translate.c > +++ b/target/arm/translate.c > @@ -282,20 +282,6 @@ static void gen_exception_internal(int excp) > tcg_temp_free_i32(tcg_excp); > } > > -static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el) > -{ > - TCGv_i32 tcg_excp = tcg_const_i32(excp); > - TCGv_i32 tcg_syn = tcg_const_i32(syndrome); > - TCGv_i32 tcg_el = tcg_const_i32(target_el); > - > - gen_helper_exception_with_syndrome(cpu_env, tcg_excp, > - tcg_syn, tcg_el); > - > - tcg_temp_free_i32(tcg_el); > - tcg_temp_free_i32(tcg_syn); > - tcg_temp_free_i32(tcg_excp); > -} > - > static void gen_step_complete_exception(DisasContext *s) > { > /* We just completed step of an insn. Move from Active-not-pending > @@ -308,8 +294,7 @@ static void gen_step_complete_exception(DisasContext *s) > * of the exception, and our syndrome information is always correct. > */ > gen_ss_advance(s); > - gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), > - default_exception_el(s)); > + gen_swstep_exception(s, 1, s->is_ldex); > s->base.is_jmp = DISAS_NORETURN; > } > > @@ -12024,8 +12009,7 @@ static bool arm_pre_translate_insn(DisasContext *dc) > * bits should be zero. > */ > assert(dc->base.num_insns == 1); > - gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), > - default_exception_el(dc)); > + gen_swstep_exception(dc, 0, 0); > dc->base.is_jmp = DISAS_NORETURN; > return true; > } >
Peter Maydell <peter.maydell@linaro.org> writes: > Factor out code to 'generate a singlestep exception', which is > currently repeated in four places. > > To do this we need to also pull the identical copies of the > gen-exception() function out of translate-a64.c and translate.c > into translate.h. > > (There is a bug in the code: we're taking the exception to the wrong > target EL. This will be simpler to fix if there's only one place to > do it.) > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > --- > target/arm/translate.h | 23 +++++++++++++++++++++++ > target/arm/translate-a64.c | 19 ++----------------- > target/arm/translate.c | 20 ++------------------ > 3 files changed, 27 insertions(+), 35 deletions(-) > > diff --git a/target/arm/translate.h b/target/arm/translate.h > index a20f6e20568..45053190baa 100644 > --- a/target/arm/translate.h > +++ b/target/arm/translate.h > @@ -2,6 +2,7 @@ > #define TARGET_ARM_TRANSLATE_H > > #include "exec/translator.h" > +#include "internals.h" > > > /* internal defines */ > @@ -232,6 +233,28 @@ static inline void gen_ss_advance(DisasContext *s) > } > } > > +static inline void gen_exception(int excp, uint32_t syndrome, > + uint32_t target_el) > +{ > + TCGv_i32 tcg_excp = tcg_const_i32(excp); > + TCGv_i32 tcg_syn = tcg_const_i32(syndrome); > + TCGv_i32 tcg_el = tcg_const_i32(target_el); > + > + gen_helper_exception_with_syndrome(cpu_env, tcg_excp, > + tcg_syn, tcg_el); > + > + tcg_temp_free_i32(tcg_el); > + tcg_temp_free_i32(tcg_syn); > + tcg_temp_free_i32(tcg_excp); > +} > + > +/* Generate an architectural singlestep exception */ > +static inline void gen_swstep_exception(DisasContext *s, int isv, int ex) > +{ > + gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, isv, ex), > + default_exception_el(s)); > +} > + > /* > * Given a VFP floating point constant encoded into an 8 bit immediate in an > * instruction, expand it to the actual constant value of the specified > diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index d3231477a27..f6729b96fd0 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -253,19 +253,6 @@ static void gen_exception_internal(int excp) > tcg_temp_free_i32(tcg_excp); > } > > -static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el) > -{ > - TCGv_i32 tcg_excp = tcg_const_i32(excp); > - TCGv_i32 tcg_syn = tcg_const_i32(syndrome); > - TCGv_i32 tcg_el = tcg_const_i32(target_el); > - > - gen_helper_exception_with_syndrome(cpu_env, tcg_excp, > - tcg_syn, tcg_el); > - tcg_temp_free_i32(tcg_el); > - tcg_temp_free_i32(tcg_syn); > - tcg_temp_free_i32(tcg_excp); > -} > - > static void gen_exception_internal_insn(DisasContext *s, int offset, int excp) > { > gen_a64_set_pc_im(s->pc - offset); > @@ -305,8 +292,7 @@ static void gen_step_complete_exception(DisasContext *s) > * of the exception, and our syndrome information is always correct. > */ > gen_ss_advance(s); > - gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), > - default_exception_el(s)); > + gen_swstep_exception(s, 1, s->is_ldex); > s->base.is_jmp = DISAS_NORETURN; > } > > @@ -14261,8 +14247,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) > * bits should be zero. > */ > assert(dc->base.num_insns == 1); > - gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), > - default_exception_el(dc)); > + gen_swstep_exception(dc, 0, 0); > dc->base.is_jmp = DISAS_NORETURN; > } else { > disas_a64_insn(env, dc); > diff --git a/target/arm/translate.c b/target/arm/translate.c > index 7853462b21b..19b9d8f2725 100644 > --- a/target/arm/translate.c > +++ b/target/arm/translate.c > @@ -282,20 +282,6 @@ static void gen_exception_internal(int excp) > tcg_temp_free_i32(tcg_excp); > } > > -static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el) > -{ > - TCGv_i32 tcg_excp = tcg_const_i32(excp); > - TCGv_i32 tcg_syn = tcg_const_i32(syndrome); > - TCGv_i32 tcg_el = tcg_const_i32(target_el); > - > - gen_helper_exception_with_syndrome(cpu_env, tcg_excp, > - tcg_syn, tcg_el); > - > - tcg_temp_free_i32(tcg_el); > - tcg_temp_free_i32(tcg_syn); > - tcg_temp_free_i32(tcg_excp); > -} > - > static void gen_step_complete_exception(DisasContext *s) > { > /* We just completed step of an insn. Move from Active-not-pending > @@ -308,8 +294,7 @@ static void gen_step_complete_exception(DisasContext *s) > * of the exception, and our syndrome information is always correct. > */ > gen_ss_advance(s); > - gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), > - default_exception_el(s)); > + gen_swstep_exception(s, 1, s->is_ldex); > s->base.is_jmp = DISAS_NORETURN; > } > > @@ -12024,8 +12009,7 @@ static bool arm_pre_translate_insn(DisasContext *dc) > * bits should be zero. > */ > assert(dc->base.num_insns == 1); > - gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), > - default_exception_el(dc)); > + gen_swstep_exception(dc, 0, 0); > dc->base.is_jmp = DISAS_NORETURN; > return true; > } -- Alex Bennée
diff --git a/target/arm/translate.h b/target/arm/translate.h index a20f6e20568..45053190baa 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -2,6 +2,7 @@ #define TARGET_ARM_TRANSLATE_H #include "exec/translator.h" +#include "internals.h" /* internal defines */ @@ -232,6 +233,28 @@ static inline void gen_ss_advance(DisasContext *s) } } +static inline void gen_exception(int excp, uint32_t syndrome, + uint32_t target_el) +{ + TCGv_i32 tcg_excp = tcg_const_i32(excp); + TCGv_i32 tcg_syn = tcg_const_i32(syndrome); + TCGv_i32 tcg_el = tcg_const_i32(target_el); + + gen_helper_exception_with_syndrome(cpu_env, tcg_excp, + tcg_syn, tcg_el); + + tcg_temp_free_i32(tcg_el); + tcg_temp_free_i32(tcg_syn); + tcg_temp_free_i32(tcg_excp); +} + +/* Generate an architectural singlestep exception */ +static inline void gen_swstep_exception(DisasContext *s, int isv, int ex) +{ + gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, isv, ex), + default_exception_el(s)); +} + /* * Given a VFP floating point constant encoded into an 8 bit immediate in an * instruction, expand it to the actual constant value of the specified diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d3231477a27..f6729b96fd0 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -253,19 +253,6 @@ static void gen_exception_internal(int excp) tcg_temp_free_i32(tcg_excp); } -static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el) -{ - TCGv_i32 tcg_excp = tcg_const_i32(excp); - TCGv_i32 tcg_syn = tcg_const_i32(syndrome); - TCGv_i32 tcg_el = tcg_const_i32(target_el); - - gen_helper_exception_with_syndrome(cpu_env, tcg_excp, - tcg_syn, tcg_el); - tcg_temp_free_i32(tcg_el); - tcg_temp_free_i32(tcg_syn); - tcg_temp_free_i32(tcg_excp); -} - static void gen_exception_internal_insn(DisasContext *s, int offset, int excp) { gen_a64_set_pc_im(s->pc - offset); @@ -305,8 +292,7 @@ static void gen_step_complete_exception(DisasContext *s) * of the exception, and our syndrome information is always correct. */ gen_ss_advance(s); - gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), - default_exception_el(s)); + gen_swstep_exception(s, 1, s->is_ldex); s->base.is_jmp = DISAS_NORETURN; } @@ -14261,8 +14247,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) * bits should be zero. */ assert(dc->base.num_insns == 1); - gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), - default_exception_el(dc)); + gen_swstep_exception(dc, 0, 0); dc->base.is_jmp = DISAS_NORETURN; } else { disas_a64_insn(env, dc); diff --git a/target/arm/translate.c b/target/arm/translate.c index 7853462b21b..19b9d8f2725 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -282,20 +282,6 @@ static void gen_exception_internal(int excp) tcg_temp_free_i32(tcg_excp); } -static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el) -{ - TCGv_i32 tcg_excp = tcg_const_i32(excp); - TCGv_i32 tcg_syn = tcg_const_i32(syndrome); - TCGv_i32 tcg_el = tcg_const_i32(target_el); - - gen_helper_exception_with_syndrome(cpu_env, tcg_excp, - tcg_syn, tcg_el); - - tcg_temp_free_i32(tcg_el); - tcg_temp_free_i32(tcg_syn); - tcg_temp_free_i32(tcg_excp); -} - static void gen_step_complete_exception(DisasContext *s) { /* We just completed step of an insn. Move from Active-not-pending @@ -308,8 +294,7 @@ static void gen_step_complete_exception(DisasContext *s) * of the exception, and our syndrome information is always correct. */ gen_ss_advance(s); - gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), - default_exception_el(s)); + gen_swstep_exception(s, 1, s->is_ldex); s->base.is_jmp = DISAS_NORETURN; } @@ -12024,8 +12009,7 @@ static bool arm_pre_translate_insn(DisasContext *dc) * bits should be zero. */ assert(dc->base.num_insns == 1); - gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), - default_exception_el(dc)); + gen_swstep_exception(dc, 0, 0); dc->base.is_jmp = DISAS_NORETURN; return true; }
Factor out code to 'generate a singlestep exception', which is currently repeated in four places. To do this we need to also pull the identical copies of the gen-exception() function out of translate-a64.c and translate.c into translate.h. (There is a bug in the code: we're taking the exception to the wrong target EL. This will be simpler to fix if there's only one place to do it.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/translate.h | 23 +++++++++++++++++++++++ target/arm/translate-a64.c | 19 ++----------------- target/arm/translate.c | 20 ++------------------ 3 files changed, 27 insertions(+), 35 deletions(-)