| Message ID | 20190805152947.28536-7-david@redhat.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | s390x: MMU changes and extensions | expand |
On 8/5/19 5:29 PM, David Hildenbrand wrote: > We already implement ESOP-1. For ESOP-2, we only have to indicate all > protection exceptions properly. Due to EDAT-1, we already indicate DAT > exceptions properly. We don't trigger KCP/ALCP/IEP exceptions yet. > > So all we have to do is set the TEID (TEC) to the right values > (bit 56, 60, 61) in case of LAP. > > We don't have any side-effects (e.g., no guarded-storage facility), > therefore, bit 64 of the TEID (TEC) is always 0. > > Signed-off-by: David Hildenbrand <david@redhat.com> > --- > target/s390x/mmu_helper.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c > index f3e988e4fd..631cc29c28 100644 > --- a/target/s390x/mmu_helper.c > +++ b/target/s390x/mmu_helper.c > @@ -333,6 +333,8 @@ int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc, > *flags |= PAGE_WRITE_INV; > if (is_low_address(vaddr) && rw == MMU_DATA_STORE) { > if (exc) { > + /* LAP sets bit 56 */ > + tec |= 0x80; > trigger_access_exception(env, PGM_PROTECTION, ilen, tec); > } > return -EACCES; > @@ -520,6 +522,8 @@ int mmu_translate_real(CPUS390XState *env, target_ulong raddr, int rw, > /* see comment in mmu_translate() how this works */ > *flags |= PAGE_WRITE_INV; > if (is_low_address(raddr) && rw == MMU_DATA_STORE) { > + /* LAP sets bit 56 */ > + tec |= 0x80; > trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, tec); > return -EACCES; > } I'd suggest to merge this with the previous patch since the other bits are only valid if bit 56 is enabled. Thomas
diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index f3e988e4fd..631cc29c28 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -333,6 +333,8 @@ int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc, *flags |= PAGE_WRITE_INV; if (is_low_address(vaddr) && rw == MMU_DATA_STORE) { if (exc) { + /* LAP sets bit 56 */ + tec |= 0x80; trigger_access_exception(env, PGM_PROTECTION, ilen, tec); } return -EACCES; @@ -520,6 +522,8 @@ int mmu_translate_real(CPUS390XState *env, target_ulong raddr, int rw, /* see comment in mmu_translate() how this works */ *flags |= PAGE_WRITE_INV; if (is_low_address(raddr) && rw == MMU_DATA_STORE) { + /* LAP sets bit 56 */ + tec |= 0x80; trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, tec); return -EACCES; }
We already implement ESOP-1. For ESOP-2, we only have to indicate all protection exceptions properly. Due to EDAT-1, we already indicate DAT exceptions properly. We don't trigger KCP/ALCP/IEP exceptions yet. So all we have to do is set the TEID (TEC) to the right values (bit 56, 60, 61) in case of LAP. We don't have any side-effects (e.g., no guarded-storage facility), therefore, bit 64 of the TEID (TEC) is always 0. Signed-off-by: David Hildenbrand <david@redhat.com> --- target/s390x/mmu_helper.c | 4 ++++ 1 file changed, 4 insertions(+)