drm/panfrost: Add errata descriptions from kbase
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Message ID 20190806202444.4827-1-alyssa.rosenzweig@collabora.com
State New
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  • drm/panfrost: Add errata descriptions from kbase
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Commit Message

Alyssa Rosenzweig Aug. 6, 2019, 8:24 p.m. UTC
While newer kbase include only the numbers of errata, older kbase
releases included one-line descriptions for each errata, which is useful
for those working on the driver. Import these descriptions. Most are
from kbase verbatim; a few I edited for clarity.

A few issues pertaining to newer models are unknown as they were not
added to kbase until after kbase began stripping these comments.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
---
 drivers/gpu/drm/panfrost/panfrost_issues.h | 80 ++++++++++++++++++++++
 1 file changed, 80 insertions(+)

Comments

Steven Price Aug. 7, 2019, 9:18 a.m. UTC | #1
On 06/08/2019 22:08, Rob Herring wrote:
> On Tue, Aug 6, 2019 at 2:25 PM Alyssa Rosenzweig
> <alyssa.rosenzweig@collabora.com> wrote:
>>
>> While newer kbase include only the numbers of errata, older kbase
>> releases included one-line descriptions for each errata, which is useful
>> for those working on the driver. Import these descriptions. Most are
>> from kbase verbatim; a few I edited for clarity.
>>
>> A few issues pertaining to newer models are unknown as they were not
>> added to kbase until after kbase began stripping these comments.
>>
>> Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
>> ---
>>   drivers/gpu/drm/panfrost/panfrost_issues.h | 80 ++++++++++++++++++++++
>>   1 file changed, 80 insertions(+)
> 
> A couple of nits below.
> 
[...]
>> +
>> +       /* TODO: Unknown */
> 
> This is Bifrost errata which is newer and I'm assuming will never have
> a description. Is there much point in any comment?

We could easily provide better comments for some of these. For example 
TMIX_8463 operates this code[1]:
> 	if (kbase_hw_has_issue(kbdev, BASE_HW_ISSUE_TMIX_8463)) {
> 		/* Ensure that L2 is not transitioning when we send the reset
> 		 * command */
> 		while (--max_loops && kbase_pm_get_trans_cores(kbdev,
> 				KBASE_PM_CORE_L2))
> 			;
> 
> 		WARN(!max_loops, "L2 power transition timed out while trying to reset\n");
> 	}
> 

So we can at least comment that the "L2 must not be transitioning when 
issuing reset command".

[1] 
https://gitlab.freedesktop.org/panfrost/mali_kbase/blob/master/driver/product/kernel/drivers/gpu/arm/midgard/backend/gpu/mali_kbase_jm_hw.c#L1197


I agree though that there's little point in "TODO: Unknown" comments.

Steve

>>          HW_ISSUE_TMIX_8463,
>> +
>> +       /* TODO: Unknown */
>>          GPUCORE_1619,
>> +
>> +       /* TODO: Unknown */
>>          HW_ISSUE_TMIX_8438,
>> +
>> +       /* TODO: Unknown */
>>          HW_ISSUE_TGOX_R1_1234,
>> +
>>          HW_ISSUE_END
>>   };
>>
>> --
>> 2.20.1
>>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>

Patch
diff mbox series

diff --git a/drivers/gpu/drm/panfrost/panfrost_issues.h b/drivers/gpu/drm/panfrost/panfrost_issues.h
index cec6dcdad..af3a31539 100644
--- a/drivers/gpu/drm/panfrost/panfrost_issues.h
+++ b/drivers/gpu/drm/panfrost/panfrost_issues.h
@@ -13,37 +13,117 @@ 
  * to care about.
  */
 enum panfrost_hw_issue {
+	/* Need way to guarantee that all previously-translated memory accesses
+	 * are commited */
 	HW_ISSUE_6367,
+
+	/* On job complete with non-done the cache is not flushed */
 	HW_ISSUE_6787,
+
+	/* Write of PRFCNT_CONFIG_MODE_MANUAL to PRFCNT_CONFIG causes a
+	 * instrumentation dump if PRFCNT_TILER_EN is enabled */
 	HW_ISSUE_8186,
+
+	/* TIB: Reports faults from a vtile which has not yet been allocated */
 	HW_ISSUE_8245,
+
+	/* uTLB deadlock could occur when writing to an invalid page at the
+	 * same time as access to a valid page in the same uTLB cache line ( ==
+	 * 4 PTEs == 16K block of mapping) */
 	HW_ISSUE_8316,
+
+	/* HT: TERMINATE for RUN command ignored if previous LOAD_DESCRIPTOR is
+	 * still executing */
 	HW_ISSUE_8394,
+
+	/* CSE: Sends a TERMINATED response for a task that should not be
+	 * terminated */
 	HW_ISSUE_8401,
+
+	/* Repeatedly Soft-stopping a job chain consisting of (Vertex Shader,
+	 * Cache Flush, Tiler) jobs causes DATA_INVALID_FAULT on tiler job. */
 	HW_ISSUE_8408,
+
+	/* Disable the Pause Buffer in the LS pipe. */
 	HW_ISSUE_8443,
+
+	/* Change in RMUs in use causes problems related with the core's SDC */
 	HW_ISSUE_8987,
+
+	/* Compute endpoint has a 4-deep queue of tasks, meaning a soft stop
+	 * won't complete until all 4 tasks have completed */
 	HW_ISSUE_9435,
+
+	/* HT: Tiler returns TERMINATED for command that hasn't been terminated
+	 */
 	HW_ISSUE_9510,
+
+	/* Occasionally the GPU will issue multiple page faults for the same
+	 * address before the MMU page table has been read by the GPU */
 	HW_ISSUE_9630,
+
+	/* RA DCD load request to SDC returns invalid load ignore causing
+	 * colour buffer mismatch */
 	HW_ISSUE_10327,
+
+	/* MMU TLB invalidation hazards */
 	HW_ISSUE_10649,
+
+	/* Missing cache flush in multi core-group configuration */
 	HW_ISSUE_10676,
+
+	/* Chicken bit on T72X for a hardware workaround in compiler */
 	HW_ISSUE_10797,
+
+	/* Soft-stopping fragment jobs might fail with TILE_RANGE_FAULT */
 	HW_ISSUE_10817,
+
+	/* Intermittent missing interrupt on job completion */
 	HW_ISSUE_10883,
+
+	/* Soft-stopping fragment jobs might fail with TILE_RANGE_ERROR
+	 * (similar to issue 10817) and can use HW_ISSUE_10817 workaround
+	 */
 	HW_ISSUE_10959,
+
+	/* Soft-stopped fragment shader job can restart with out-of-bound
+	 * restart index
+	 */
 	HW_ISSUE_10969,
+
+	/* Race condition can cause tile list corruption */
 	HW_ISSUE_11020,
+
+	/* Write buffer can cause tile list corruption */
 	HW_ISSUE_11024,
+
+	/* Pause buffer can cause a fragment job hang */
 	HW_ISSUE_11035,
+
+	/* TODO: Unknown */
 	HW_ISSUE_11056,
+
+	/* Clear encoder state for a hard stopped fragment job which is AFBC
+	 * encoded by soft resetting the GPU. Only for T76X r0p0, r0p1 and
+	 * r0p1_50rel0
+	 */
 	HW_ISSUE_T76X_3542,
+
+	/* Keep tiler module clock on to prevent GPU stall */
 	HW_ISSUE_T76X_3953,
+
+	/* TODO: Unknown */
 	HW_ISSUE_TMIX_8463,
+
+	/* TODO: Unknown */
 	GPUCORE_1619,
+
+	/* TODO: Unknown */
 	HW_ISSUE_TMIX_8438,
+
+	/* TODO: Unknown */
 	HW_ISSUE_TGOX_R1_1234,
+
 	HW_ISSUE_END
 };