diff mbox series

x86/boot: Set Accessed bits in boot_cpu_{, compat_}gdt_table[]

Message ID 20190807113439.12802-1-andrew.cooper3@citrix.com (mailing list archive)
State New, archived
Headers show
Series x86/boot: Set Accessed bits in boot_cpu_{, compat_}gdt_table[] | expand

Commit Message

Andrew Cooper Aug. 7, 2019, 11:34 a.m. UTC 
There is no point causing the CPU to performed a locked update of the
descriptors on first use.

Reported-by: Jan Beulich <jbeulich@suse.com>
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
CC: Jan Beulich <JBeulich@suse.com>
CC: Wei Liu <wl@xen.org>
CC: Roger Pau Monné <roger.pau@citrix.com>
---
 xen/arch/x86/boot/x86_64.S | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

Comments

Jan Beulich Aug. 7, 2019, 11:53 a.m. UTC | #1 
On 07.08.2019 13:34, Andrew Cooper wrote:
> There is no point causing the CPU to performed a locked update of the
> descriptors on first use.
> 
> Reported-by: Jan Beulich <jbeulich@suse.com>
> Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>

Reviewed-by: Jan Beulich <jbeulich@suse.com>
diff mbox series

Patch

diff --git a/xen/arch/x86/boot/x86_64.S b/xen/arch/x86/boot/x86_64.S
index cf47e019f5..0eaf9d2a07 100644
--- a/xen/arch/x86/boot/x86_64.S
+++ b/xen/arch/x86/boot/x86_64.S
@@ -55,13 +55,13 @@  GLOBAL(stack_start)
         .align PAGE_SIZE, 0
 GLOBAL(boot_cpu_gdt_table)
         .quad 0x0000000000000000     /* unused */
-        .quad 0x00af9a000000ffff     /* 0xe008 ring 0 code, 64-bit mode   */
-        .quad 0x00cf92000000ffff     /* 0xe010 ring 0 data                */
+        .quad 0x00af9b000000ffff     /* 0xe008 ring 0 code, 64-bit mode   */
+        .quad 0x00cf93000000ffff     /* 0xe010 ring 0 data                */
         .quad 0x0000000000000000     /* reserved                          */
-        .quad 0x00cffa000000ffff     /* 0xe023 ring 3 code, compatibility */
-        .quad 0x00cff2000000ffff     /* 0xe02b ring 3 data                */
-        .quad 0x00affa000000ffff     /* 0xe033 ring 3 code, 64-bit mode   */
-        .quad 0x00cf9a000000ffff     /* 0xe038 ring 0 code, compatibility */
+        .quad 0x00cffb000000ffff     /* 0xe023 ring 3 code, compatibility */
+        .quad 0x00cff3000000ffff     /* 0xe02b ring 3 data                */
+        .quad 0x00affb000000ffff     /* 0xe033 ring 3 code, 64-bit mode   */
+        .quad 0x00cf9b000000ffff     /* 0xe038 ring 0 code, compatibility */
         .fill (PER_CPU_GDT_ENTRY - __HYPERVISOR_CS32 / 8 - 1), 8, 0
         .quad 0x0000910000000000     /* per-CPU entry (limit == cpu)      */
 
@@ -70,13 +70,13 @@  GLOBAL(boot_cpu_gdt_table)
 /*     (compatibility) machine->physical mapping table lives there.       */
 GLOBAL(boot_cpu_compat_gdt_table)
         .quad 0x0000000000000000     /* unused */
-        .quad 0x00af9a000000ffff     /* 0xe008 ring 0 code, 64-bit mode   */
-        .quad 0x00cf92000000ffff     /* 0xe010 ring 0 data                */
-        .quad 0x00cfba000000ffff     /* 0xe019 ring 1 code, compatibility */
-        .quad 0x00cfb2000000ffff     /* 0xe021 ring 1 data                */
-        .quad 0x00cffa000000ffff     /* 0xe02b ring 3 code, compatibility */
-        .quad 0x00cff2000000ffff     /* 0xe033 ring 3 data                */
-        .quad 0x00cf9a000000ffff     /* 0xe038 ring 0 code, compatibility */
+        .quad 0x00af9b000000ffff     /* 0xe008 ring 0 code, 64-bit mode   */
+        .quad 0x00cf93000000ffff     /* 0xe010 ring 0 data                */
+        .quad 0x00cfbb000000ffff     /* 0xe019 ring 1 code, compatibility */
+        .quad 0x00cfb3000000ffff     /* 0xe021 ring 1 data                */
+        .quad 0x00cffb000000ffff     /* 0xe02b ring 3 code, compatibility */
+        .quad 0x00cff3000000ffff     /* 0xe033 ring 3 data                */
+        .quad 0x00cf9b000000ffff     /* 0xe038 ring 0 code, compatibility */
         .fill (PER_CPU_GDT_ENTRY - __HYPERVISOR_CS32 / 8 - 1), 8, 0
         .quad 0x0000910000000000     /* per-CPU entry (limit == cpu)      */
         .align PAGE_SIZE, 0