| Message ID | 20190808131448.349161-2-tmaimon77@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | spi: add NPCM FIU controller driver | expand |
On Thu, Aug 08, 2019 at 04:14:47PM +0300, Tomer Maimon wrote: > Added device tree binding documentation for Nuvoton BMC > NPCM Flash Interface Unit(FIU) SPI master controller > using SPI-MEM interface. > > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> > --- > .../bindings/spi/nuvoton,npcm-fiu.txt | 47 +++++++++++++++++++ > 1 file changed, 47 insertions(+) > create mode 100644 Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt > > diff --git a/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt b/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt > new file mode 100644 > index 000000000000..ab37aae91d19 > --- /dev/null > +++ b/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt > @@ -0,0 +1,47 @@ > +* Nuvoton FLASH Interface Unit (FIU) SPI Controller > + > +NPCM FIU supports single, dual and quad communication interface. > + > +The NPCM7XX supports three FIU modules, > +FIU0 and FIUx supports two chip selects, > +FIU3 support four chip select. > + > +Required properties: > + - compatible : "nuvoton,npcm750-fiu" for the NPCM7XX BMC > + - #address-cells : should be 1. > + - #size-cells : should be 0. > + - reg : the first contains the register location and length, > + the second contains the memory mapping address and length > + - reg-names: Should contain the reg names "control" and "memory" > + - clocks : phandle of FIU reference clock. > + > +Required properties in case the pins can be muxed: > + - pinctrl-names : a pinctrl state named "default" must be defined. > + - pinctrl-0 : phandle referencing pin configuration of the device. > + > +Optional property: > + - spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD. Is this something standard? If not, add a vendor prefix. > + > +Aliases: > +- All the FIU controller nodes should be represented in the aliases node using > + the following format 'fiu{n}' where n is a unique number for the alias. > + In the NPCM7XX BMC: > + fiu0 represent fiu 0 controller > + fiu1 represent fiu 3 controller > + fiu2 represent fiu x controller > + > +Example: > +fiu3: fiu@c00000000 { spi@... > + compatible = "nuvoton,npcm750-fiu"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>; > + reg-names = "control", "memory"; > + clocks = <&clk NPCM7XX_CLK_AHB>; > + pinctrl-names = "default"; > + pinctrl-0 = <&spi3_pins>; > + spi-nor@0 { > + ... > + }; > +}; > + > -- > 2.18.0 >
diff --git a/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt b/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt new file mode 100644 index 000000000000..ab37aae91d19 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt @@ -0,0 +1,47 @@ +* Nuvoton FLASH Interface Unit (FIU) SPI Controller + +NPCM FIU supports single, dual and quad communication interface. + +The NPCM7XX supports three FIU modules, +FIU0 and FIUx supports two chip selects, +FIU3 support four chip select. + +Required properties: + - compatible : "nuvoton,npcm750-fiu" for the NPCM7XX BMC + - #address-cells : should be 1. + - #size-cells : should be 0. + - reg : the first contains the register location and length, + the second contains the memory mapping address and length + - reg-names: Should contain the reg names "control" and "memory" + - clocks : phandle of FIU reference clock. + +Required properties in case the pins can be muxed: + - pinctrl-names : a pinctrl state named "default" must be defined. + - pinctrl-0 : phandle referencing pin configuration of the device. + +Optional property: + - spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD. + +Aliases: +- All the FIU controller nodes should be represented in the aliases node using + the following format 'fiu{n}' where n is a unique number for the alias. + In the NPCM7XX BMC: + fiu0 represent fiu 0 controller + fiu1 represent fiu 3 controller + fiu2 represent fiu x controller + +Example: +fiu3: fiu@c00000000 { + compatible = "nuvoton,npcm750-fiu"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>; + reg-names = "control", "memory"; + clocks = <&clk NPCM7XX_CLK_AHB>; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pins>; + spi-nor@0 { + ... + }; +}; +
Added device tree binding documentation for Nuvoton BMC NPCM Flash Interface Unit(FIU) SPI master controller using SPI-MEM interface. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> --- .../bindings/spi/nuvoton,npcm-fiu.txt | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt