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Mon, 12 Aug 2019 14:21:36 +0000 From: Philippe Schenker To: Marcel Ziswiler , Max Krummenacher , "stefan@agner.ch" , "devicetree@vger.kernel.org" , Rob Herring , Shawn Guo , Mark Rutland , =?iso-8859-2?q?Michal_Vok=E1=E8?= , Fabio Estevam Subject: [PATCH v4 14/21] ARM: dts: imx6ull-colibri: Add sleep mode to fec Thread-Topic: [PATCH v4 14/21] ARM: dts: imx6ull-colibri: Add sleep mode to fec Thread-Index: AQHVURk/ykft4ua73EKmDHr197vAbw== Date: Mon, 12 Aug 2019 14:21:36 +0000 Message-ID: <20190812142105.1995-15-philippe.schenker@toradex.com> References: <20190812142105.1995-1-philippe.schenker@toradex.com> In-Reply-To: <20190812142105.1995-1-philippe.schenker@toradex.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1P194CA0055.EURP194.PROD.OUTLOOK.COM (2603:10a6:803:3c::44) To VI1PR0502MB3965.eurprd05.prod.outlook.com (2603:10a6:803:23::29) authentication-results: spf=none (sender IP is ) smtp.mailfrom=philippe.schenker@toradex.com; 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Signed-off-by: Philippe Schenker Acked-by: Marcel Ziswiler Reviewed-by: Oleksandr Suvorov --- Changes in v4: - Add Marcel Ziswiler's Ack Changes in v3: None Changes in v2: None arch/arm/boot/dts/imx6ull-colibri.dtsi | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index d56728f03c35..1019ce69a242 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -62,8 +62,9 @@ }; &fec2 { - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_enet2>; + pinctrl-1 = <&pinctrl_enet2_sleep>; phy-mode = "rmii"; phy-handle = <ðphy1>; status = "okay"; @@ -220,6 +221,21 @@ >; }; + pinctrl_enet2_sleep: enet2sleepgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0 + MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0 + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x0 + MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x0 + MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x0 + MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0 + MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x0 + MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x0 + >; + }; + pinctrl_ecspi1_cs: ecspi1-cs-grp { fsl,pins = < MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x000a0