diff mbox series

[v3,05/28] xen/arm64: head: Setup TTBR_EL2 in enable_mmu() and add missing isb

Message ID 20190812173019.11956-6-julien.grall@arm.com (mailing list archive)
State Superseded
Headers show
Series xen/arm: Rework head.S to make it more compliant with the Arm Arm | expand

Commit Message

Julien Grall Aug. 12, 2019, 5:29 p.m. UTC 
At the moment, TTBR_EL2 is setup in create_page_tables(). This is fine
as it is called by every CPUs.

However, such assumption may not hold in the future. To make change
easier, the TTBR_EL2 is not setup in enable_mmu().

Take the opportunity to add the missing isb() to ensure the TTBR_EL2 is
seen before the MMU is turned on.

Signed-off-by: Julien Grall <julien.grall@arm.com>
Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>

---
    Changes in v3:
        - Add Stefano's acked-by

    Changes in v2:
        - Patch added
---
 xen/arch/arm/arm64/head.S | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
index 925fb93e58..9b703e79ce 100644
--- a/xen/arch/arm/arm64/head.S
+++ b/xen/arch/arm/arm64/head.S
@@ -507,9 +507,7 @@  create_page_tables:
         cmp   x19, #XEN_VIRT_START
         cset  x25, eq                /* x25 := identity map in place, or not */
 
-        /* Write Xen's PT's paddr into TTBR0_EL2 */
         load_paddr x4, boot_pgtable
-        msr   TTBR0_EL2, x4
 
         /* Setup boot_pgtable: */
         load_paddr x1, boot_first
@@ -637,6 +635,11 @@  enable_mmu:
         tlbi  alle2                  /* Flush hypervisor TLBs */
         dsb   nsh
 
+        /* Write Xen's PT's paddr into TTBR0_EL2 */
+        load_paddr x0, boot_pgtable
+        msr   TTBR0_EL2, x0
+        isb
+
         mrs   x0, SCTLR_EL2
         orr   x0, x0, #SCTLR_Axx_ELx_M  /* Enable MMU */
         orr   x0, x0, #SCTLR_Axx_ELx_C  /* Enable D-cache */