clk: imx8mn: fix int pll clk gate
diff mbox series

Message ID 20190814015312.11711-1-peng.fan@nxp.com
State New
Headers show
Series
  • clk: imx8mn: fix int pll clk gate
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Commit Message

Peng Fan Aug. 14, 2019, 1:53 a.m. UTC
From: Peng Fan <peng.fan@nxp.com>

To Frac pll, the gate shift is 13, however to Int PLL the gate shift
is 11.

Cc: <stable@vger.kernel.org>
Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
---
 drivers/clk/imx/clk-imx8mn.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

Comments

Stephen Boyd Aug. 16, 2019, 6:02 p.m. UTC | #1
Quoting peng.fan@nxp.com (2019-08-13 18:53:12)
> From: Peng Fan <peng.fan@nxp.com>
> 
> To Frac pll, the gate shift is 13, however to Int PLL the gate shift
> is 11.
> 
> Cc: <stable@vger.kernel.org>
> Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver")
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
> ---

This is a fix for a change in -next. Why is stable Cced?
Peng Fan Aug. 19, 2019, 1:05 a.m. UTC | #2
Hi Stephen,

> Subject: Re: [PATCH] clk: imx8mn: fix int pll clk gate
> 
> Quoting peng.fan@nxp.com (2019-08-13 18:53:12)
> > From: Peng Fan <peng.fan@nxp.com>
> >
> > To Frac pll, the gate shift is 13, however to Int PLL the gate shift
> > is 11.
> >
> > Cc: <stable@vger.kernel.org>
> > Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver")
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > Reviewed-by: Jacky Bai <ping.bai@nxp.com>
> > ---
> 
> This is a fix for a change in -next. Why is stable Cced?

Sorry, that was added by mistaken. Should I resend v2 to drop it?

Thanks,
Peng.
Shawn Guo Aug. 19, 2019, 11:59 a.m. UTC | #3
On Mon, Aug 19, 2019 at 01:05:42AM +0000, Peng Fan wrote:
> Hi Stephen,
> 
> > Subject: Re: [PATCH] clk: imx8mn: fix int pll clk gate
> > 
> > Quoting peng.fan@nxp.com (2019-08-13 18:53:12)
> > > From: Peng Fan <peng.fan@nxp.com>
> > >
> > > To Frac pll, the gate shift is 13, however to Int PLL the gate shift
> > > is 11.
> > >
> > > Cc: <stable@vger.kernel.org>
> > > Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver")
> > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > Reviewed-by: Jacky Bai <ping.bai@nxp.com>
> > > ---
> > 
> > This is a fix for a change in -next. Why is stable Cced?
> 
> Sorry, that was added by mistaken. Should I resend v2 to drop it?

Applied with both stable and Fixes tag dropped, as the commit ID is
unstable before it lands on mainline.

Shawn

Patch
diff mbox series

diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index ecd1062f6847..c5838710e1d8 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -436,12 +436,12 @@  static int imx8mn_clocks_probe(struct platform_device *pdev)
 	clks[IMX8MN_AUDIO_PLL2_OUT] = imx_clk_gate("audio_pll2_out", "audio_pll2_bypass", base + 0x14, 13);
 	clks[IMX8MN_VIDEO_PLL1_OUT] = imx_clk_gate("video_pll1_out", "video_pll1_bypass", base + 0x28, 13);
 	clks[IMX8MN_DRAM_PLL_OUT] = imx_clk_gate("dram_pll_out", "dram_pll_bypass", base + 0x50, 13);
-	clks[IMX8MN_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 13);
-	clks[IMX8MN_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 13);
-	clks[IMX8MN_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 13);
-	clks[IMX8MN_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 13);
-	clks[IMX8MN_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 13);
-	clks[IMX8MN_SYS_PLL3_OUT] = imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 13);
+	clks[IMX8MN_GPU_PLL_OUT] = imx_clk_gate("gpu_pll_out", "gpu_pll_bypass", base + 0x64, 11);
+	clks[IMX8MN_VPU_PLL_OUT] = imx_clk_gate("vpu_pll_out", "vpu_pll_bypass", base + 0x74, 11);
+	clks[IMX8MN_ARM_PLL_OUT] = imx_clk_gate("arm_pll_out", "arm_pll_bypass", base + 0x84, 11);
+	clks[IMX8MN_SYS_PLL1_OUT] = imx_clk_gate("sys_pll1_out", "sys_pll1_bypass", base + 0x94, 11);
+	clks[IMX8MN_SYS_PLL2_OUT] = imx_clk_gate("sys_pll2_out", "sys_pll2_bypass", base + 0x104, 11);
+	clks[IMX8MN_SYS_PLL3_OUT] = imx_clk_gate("sys_pll3_out", "sys_pll3_bypass", base + 0x114, 11);
 
 	/* SYS PLL fixed output */
 	clks[IMX8MN_SYS_PLL1_40M] = imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20);