diff mbox series

[v1] s390x/tcg: Fix VERIM with 32/64 bit elements

Message ID 20190814151242.27199-1-david@redhat.com (mailing list archive)
State New, archived
Headers show
Series [v1] s390x/tcg: Fix VERIM with 32/64 bit elements | expand

Commit Message

David Hildenbrand Aug. 14, 2019, 3:12 p.m. UTC
Wrong order of operands. The constant always comes last. Makes QEMU crash
reliably on specific git fetch invocations.

Reported-by: Stefano Brivio <sbrivio@redhat.com>
Signed-off-by: David Hildenbrand <david@redhat.com>
---

I guess it is too late for 4.1 :(

---
 target/s390x/translate_vx.inc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Cornelia Huck Aug. 14, 2019, 3:41 p.m. UTC | #1
On Wed, 14 Aug 2019 17:12:42 +0200
David Hildenbrand <david@redhat.com> wrote:

> Wrong order of operands. The constant always comes last. Makes QEMU crash
> reliably on specific git fetch invocations.
> 
> Reported-by: Stefano Brivio <sbrivio@redhat.com>
> Signed-off-by: David Hildenbrand <david@redhat.com>
> ---
> 
> I guess it is too late for 4.1 :(

Yup :(

But cc:stable worthy, I guess.

> 
> ---
>  target/s390x/translate_vx.inc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
> index 41d5cf869f..0caddb3958 100644
> --- a/target/s390x/translate_vx.inc.c
> +++ b/target/s390x/translate_vx.inc.c
> @@ -213,7 +213,7 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
>                         vec_full_reg_offset(v3), ptr, 16, 16, data, fn)
>  #define gen_gvec_3i(v1, v2, v3, c, gen) \
>      tcg_gen_gvec_3i(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
> -                    vec_full_reg_offset(v3), c, 16, 16, gen)
> +                    vec_full_reg_offset(v3), 16, 16, c, gen)
>  #define gen_gvec_4(v1, v2, v3, v4, gen) \
>      tcg_gen_gvec_4(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
>                     vec_full_reg_offset(v3), vec_full_reg_offset(v4), \
David Hildenbrand Aug. 14, 2019, 3:43 p.m. UTC | #2
On 14.08.19 17:41, Cornelia Huck wrote:
> On Wed, 14 Aug 2019 17:12:42 +0200
> David Hildenbrand <david@redhat.com> wrote:
> 
>> Wrong order of operands. The constant always comes last. Makes QEMU crash
>> reliably on specific git fetch invocations.
>>
>> Reported-by: Stefano Brivio <sbrivio@redhat.com>
>> Signed-off-by: David Hildenbrand <david@redhat.com>
>> ---
>>
>> I guess it is too late for 4.1 :(
> 
> Yup :(
> 
> But cc:stable worthy, I guess.
> 

Yes. Added this bug to

https://wiki.qemu.org/Planning/4.1#Not_yet_fixed_in_any_rc

>>
>> ---
>>  target/s390x/translate_vx.inc.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
>> index 41d5cf869f..0caddb3958 100644
>> --- a/target/s390x/translate_vx.inc.c
>> +++ b/target/s390x/translate_vx.inc.c
>> @@ -213,7 +213,7 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
>>                         vec_full_reg_offset(v3), ptr, 16, 16, data, fn)
>>  #define gen_gvec_3i(v1, v2, v3, c, gen) \
>>      tcg_gen_gvec_3i(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
>> -                    vec_full_reg_offset(v3), c, 16, 16, gen)
>> +                    vec_full_reg_offset(v3), 16, 16, c, gen)
>>  #define gen_gvec_4(v1, v2, v3, v4, gen) \
>>      tcg_gen_gvec_4(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
>>                     vec_full_reg_offset(v3), vec_full_reg_offset(v4), \
>
Cornelia Huck Aug. 15, 2019, 9 a.m. UTC | #3
On Wed, 14 Aug 2019 17:12:42 +0200
David Hildenbrand <david@redhat.com> wrote:

> Wrong order of operands. The constant always comes last. Makes QEMU crash
> reliably on specific git fetch invocations.
> 
> Reported-by: Stefano Brivio <sbrivio@redhat.com>
> Signed-off-by: David Hildenbrand <david@redhat.com>
> ---
> 
> I guess it is too late for 4.1 :(
> 
> ---
>  target/s390x/translate_vx.inc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
> index 41d5cf869f..0caddb3958 100644
> --- a/target/s390x/translate_vx.inc.c
> +++ b/target/s390x/translate_vx.inc.c
> @@ -213,7 +213,7 @@ static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
>                         vec_full_reg_offset(v3), ptr, 16, 16, data, fn)
>  #define gen_gvec_3i(v1, v2, v3, c, gen) \
>      tcg_gen_gvec_3i(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
> -                    vec_full_reg_offset(v3), c, 16, 16, gen)
> +                    vec_full_reg_offset(v3), 16, 16, c, gen)
>  #define gen_gvec_4(v1, v2, v3, v4, gen) \
>      tcg_gen_gvec_4(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
>                     vec_full_reg_offset(v3), vec_full_reg_offset(v4), \

Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Fixes: 5c4b0ab460ef ("s390x/tcg: Implement VECTOR ELEMENT ROTATE AND INSERT UNDER MASK")
Cc: qemu-stable@nongnu.org

Thanks, applied.
diff mbox series

Patch

diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.inc.c
index 41d5cf869f..0caddb3958 100644
--- a/target/s390x/translate_vx.inc.c
+++ b/target/s390x/translate_vx.inc.c
@@ -213,7 +213,7 @@  static void get_vec_element_ptr_i64(TCGv_ptr ptr, uint8_t reg, TCGv_i64 enr,
                        vec_full_reg_offset(v3), ptr, 16, 16, data, fn)
 #define gen_gvec_3i(v1, v2, v3, c, gen) \
     tcg_gen_gvec_3i(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
-                    vec_full_reg_offset(v3), c, 16, 16, gen)
+                    vec_full_reg_offset(v3), 16, 16, c, gen)
 #define gen_gvec_4(v1, v2, v3, v4, gen) \
     tcg_gen_gvec_4(vec_full_reg_offset(v1), vec_full_reg_offset(v2), \
                    vec_full_reg_offset(v3), vec_full_reg_offset(v4), \