| Message ID | 1565877215-1331-1-git-send-email-tanmay@marvell.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | coresight: Add ETM4.1 support for ThunderX2 | expand |
Same comment as the previous patch along with the following... On Thu, Aug 15, 2019 at 01:53:46PM +0000, Tanmay Vilas Kumar Jagdale wrote: > Add ETM4.1 periperhal ID for Marvell's ThunderX2 chip. > > Signed-off-by: Tanmay Jagdale <tanmay@marvell.com> > --- > drivers/hwtracing/coresight/coresight-etm4x.c | 2 ++ > drivers/hwtracing/coresight/coresight-etm4x.h | 1 + > 2 files changed, 3 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c > index 7bcac8896fc1..ac3bd617907b 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x.c > @@ -58,6 +58,7 @@ static bool etm4_arch_supported(u8 arch) > /* Mask out the minor version number */ > switch (arch & 0xf0) { > case ETM_ARCH_V4: > + case ETM_ARCH_V4_1: Why add ETM_ARCH_V4_1 when the switch statement strips off the first byte? Look at[1], someone already added support for 4.2. [1]. 5666dfd1d8a4 coresight: etm4x: Add support to enable ETMv4.2 > break; > default: > return false; > @@ -1196,6 +1197,7 @@ static const struct amba_id etm4_ids[] = { > CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */ > CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */ > CS_AMBA_ID(0x000bb959), /* Cortex-A73 */ > + CS_AMBA_ID(0x000cc0af), /* Marvell ThunderX2 */ I suspect this processor also has "coresight-cpu-debug" IPs. If that is the case it is very possible they both have the same CID and a UCI (see next line) is required. > CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4), /* Cortex-A35 */ > {}, > }; Thanks, Mathieu > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index 4523f10ddd0f..03369e56b2eb 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -137,6 +137,7 @@ > #define ETM_MAX_SS_CMP 8 > > #define ETM_ARCH_V4 0x40 > +#define ETM_ARCH_V4_1 0x41 > #define ETMv4_SYNC_MASK 0x1F > #define ETM_CYC_THRESHOLD_MASK 0xFFF > #define ETM_CYC_THRESHOLD_DEFAULT 0x100 > -- > 2.17.1 >
Hi Mathieu, > Same comment as the previous patch along with the following... > > On Thu, Aug 15, 2019 at 01:53:46PM +0000, Tanmay Vilas Kumar Jagdale wrote: > > Add ETM4.1 periperhal ID for Marvell's ThunderX2 chip. > > > > Signed-off-by: Tanmay Jagdale <tanmay@marvell.com> > > --- > > drivers/hwtracing/coresight/coresight-etm4x.c | 2 ++ > > drivers/hwtracing/coresight/coresight-etm4x.h | 1 + > > 2 files changed, 3 insertions(+) > > > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c > > b/drivers/hwtracing/coresight/coresight-etm4x.c > > index 7bcac8896fc1..ac3bd617907b 100644 > > --- a/drivers/hwtracing/coresight/coresight-etm4x.c > > +++ b/drivers/hwtracing/coresight/coresight-etm4x.c > > @@ -58,6 +58,7 @@ static bool etm4_arch_supported(u8 arch) > > /* Mask out the minor version number */ > > switch (arch & 0xf0) { > > case ETM_ARCH_V4: > > + case ETM_ARCH_V4_1: > > Why add ETM_ARCH_V4_1 when the switch statement strips off the first byte? > > Look at[1], someone already added support for 4.2. > > [1]. 5666dfd1d8a4 coresight: etm4x: Add support to enable ETMv4.2 > > > > break; > > default: > > return false; > > @@ -1196,6 +1197,7 @@ static const struct amba_id etm4_ids[] = { > > CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */ > > CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */ > > CS_AMBA_ID(0x000bb959), /* Cortex-A73 */ > > + CS_AMBA_ID(0x000cc0af), /* Marvell ThunderX2 */ > > I suspect this processor also has "coresight-cpu-debug" IPs. If that is the > case it is very possible they both have the same CID and a UCI (see next line) > is required. > Yes, our processor has the coresight-cpu-debug IP. Currently I am working with the hardware team to test this feature. Once that is done I will post a patch that supports it. In the meantime I will post a v2 patch for ETMv4 with UCI. Hope that is okay. > > CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4), /* Cortex-A35 */ > > {}, > > }; > > Thanks, > Mathieu > > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h > > b/drivers/hwtracing/coresight/coresight-etm4x.h > > index 4523f10ddd0f..03369e56b2eb 100644 > > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > > @@ -137,6 +137,7 @@ > > #define ETM_MAX_SS_CMP 8 > > > > #define ETM_ARCH_V4 0x40 > > +#define ETM_ARCH_V4_1 0x41 > > #define ETMv4_SYNC_MASK 0x1F > > #define ETM_CYC_THRESHOLD_MASK 0xFFF > > #define ETM_CYC_THRESHOLD_DEFAULT 0x100 > > -- > > 2.17.1 > > Thanks, Tanmay
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 7bcac8896fc1..ac3bd617907b 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -58,6 +58,7 @@ static bool etm4_arch_supported(u8 arch) /* Mask out the minor version number */ switch (arch & 0xf0) { case ETM_ARCH_V4: + case ETM_ARCH_V4_1: break; default: return false; @@ -1196,6 +1197,7 @@ static const struct amba_id etm4_ids[] = { CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */ CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */ CS_AMBA_ID(0x000bb959), /* Cortex-A73 */ + CS_AMBA_ID(0x000cc0af), /* Marvell ThunderX2 */ CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4), /* Cortex-A35 */ {}, }; diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h index 4523f10ddd0f..03369e56b2eb 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -137,6 +137,7 @@ #define ETM_MAX_SS_CMP 8 #define ETM_ARCH_V4 0x40 +#define ETM_ARCH_V4_1 0x41 #define ETMv4_SYNC_MASK 0x1F #define ETM_CYC_THRESHOLD_MASK 0xFFF #define ETM_CYC_THRESHOLD_DEFAULT 0x100
Add ETM4.1 periperhal ID for Marvell's ThunderX2 chip. Signed-off-by: Tanmay Jagdale <tanmay@marvell.com> --- drivers/hwtracing/coresight/coresight-etm4x.c | 2 ++ drivers/hwtracing/coresight/coresight-etm4x.h | 1 + 2 files changed, 3 insertions(+)