| Message ID | 1565915925-21009-4-git-send-email-Anson.Huang@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [V6,1/4] clocksource: imx-sysctr: Add internal clock divider handle | expand |
On 16/08/2019 02:38, Anson Huang wrote: > Enable i.MX8MM cpu-idle using generic ARM cpu-idle driver, 2 states > are supported, details as below: > > root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state0/name > WFI > root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state0/usage > 3973 > root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state1/name > cpu-pd-wait > root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state1/usage > 6647 > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Hi Anson, I've applied the patches 1-3 but this one does not apply. You can either respin it against tip/timers/core and take it through Shawn's tree. If the later, you can add my Acked-by. -- Daniel
Hi, Daniel/Shawn > On 16/08/2019 02:38, Anson Huang wrote: > > Enable i.MX8MM cpu-idle using generic ARM cpu-idle driver, 2 states > > are supported, details as below: > > > > root@imx8mmevk:~# cat > /sys/devices/system/cpu/cpu0/cpuidle/state0/name > > WFI > > root@imx8mmevk:~# cat > > /sys/devices/system/cpu/cpu0/cpuidle/state0/usage > > 3973 > > root@imx8mmevk:~# cat > /sys/devices/system/cpu/cpu0/cpuidle/state1/name > > cpu-pd-wait > > root@imx8mmevk:~# cat > > /sys/devices/system/cpu/cpu0/cpuidle/state1/usage > > 6647 > > > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > > Hi Anson, > > I've applied the patches 1-3 but this one does not apply. Thanks. > > You can either respin it against tip/timers/core and take it through Shawn's > tree. If the later, you can add my Acked-by. Hi, Shawn Can you take this patch and add below Acked-by? It should can be applied to your tree directly. Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Thanks, Anson
Hi, Shawn > > On 16/08/2019 02:38, Anson Huang wrote: > > > Enable i.MX8MM cpu-idle using generic ARM cpu-idle driver, 2 states > > > are supported, details as below: > > > > > > root@imx8mmevk:~# cat > > /sys/devices/system/cpu/cpu0/cpuidle/state0/name > > > WFI > > > root@imx8mmevk:~# cat > > > /sys/devices/system/cpu/cpu0/cpuidle/state0/usage > > > 3973 > > > root@imx8mmevk:~# cat > > /sys/devices/system/cpu/cpu0/cpuidle/state1/name > > > cpu-pd-wait > > > root@imx8mmevk:~# cat > > > /sys/devices/system/cpu/cpu0/cpuidle/state1/usage > > > 6647 > > > > > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> > > > > Hi Anson, > > > > I've applied the patches 1-3 but this one does not apply. > > Thanks. > > > > > You can either respin it against tip/timers/core and take it through > > Shawn's tree. If the later, you can add my Acked-by. > > Hi, Shawn > Can you take this patch and add below Acked-by? It should can be > applied to your tree directly. > > Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Sorry that I just found this patch can NOT be applied to your for-next tree neither, so I redo the patch against your for-next tree, so you can just skip this patch series now (as Daniel already picked the rest 3 patches) and take that patch I just sent, link as below: https://patchwork.kernel.org/patch/11097471/ Thanks, Anson
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 94433c53..9b2dc12 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -44,6 +44,19 @@ #address-cells = <1>; #size-cells = <0>; + idle-states { + entry-method = "psci"; + + cpu_pd_wait: cpu-pd-wait { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0010033>; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + }; + }; + A53_0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a53"; @@ -56,6 +69,7 @@ nvmem-cells = <&cpu_speed_grade>; nvmem-cell-names = "speed_grade"; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; }; A53_1: cpu@1 { @@ -68,6 +82,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; }; A53_2: cpu@2 { @@ -80,6 +95,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; }; A53_3: cpu@3 { @@ -92,6 +108,7 @@ next-level-cache = <&A53_L2>; operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; + cpu-idle-states = <&cpu_pd_wait>; }; A53_L2: l2-cache0 {
Enable i.MX8MM cpu-idle using generic ARM cpu-idle driver, 2 states are supported, details as below: root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state0/name WFI root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state0/usage 3973 root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state1/name cpu-pd-wait root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state1/usage 6647 Signed-off-by: Anson Huang <Anson.Huang@nxp.com> --- Changes since V5: - improve state1 idle name to better match PSCI doc; - remove wakeup-latency-us property as it is NOT necessary when entry-latency-us/exit-latency-us exist. --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)