| Message ID | 20190816012343.36433-3-daniele.ceraolospurio@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Some more display uncore prep work | expand |
On Thu, Aug 15, 2019 at 6:23 PM Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> wrote: > > To remove the dependency between the GT headers and i915_reg.h, move the > definition of the engine IDs/classes to intel_engine_types.h > > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Lucas De Marchi > --- > drivers/gpu/drm/i915/gt/intel_engine_types.h | 20 +++++++++++++++ > drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 + > drivers/gpu/drm/i915/i915_reg.h | 27 +++----------------- > 3 files changed, 24 insertions(+), 24 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h > index a0f372807dd4..8f10c5ffd68d 100644 > --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h > +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h > @@ -26,6 +26,26 @@ > #include "intel_wakeref.h" > #include "intel_workarounds_types.h" > > +/* Legacy HW Engine ID */ > + > +#define RCS0_HW 0 > +#define VCS0_HW 1 > +#define BCS0_HW 2 > +#define VECS0_HW 3 > +#define VCS1_HW 4 > +#define VCS2_HW 6 > +#define VCS3_HW 7 > +#define VECS1_HW 12 > + > +/* Gen11+ HW Engine class + instance */ > +#define RENDER_CLASS 0 > +#define VIDEO_DECODE_CLASS 1 > +#define VIDEO_ENHANCEMENT_CLASS 2 > +#define COPY_ENGINE_CLASS 3 > +#define OTHER_CLASS 4 > +#define MAX_ENGINE_CLASS 4 > +#define MAX_ENGINE_INSTANCE 3 > + > #define I915_MAX_SLICES 3 > #define I915_MAX_SUBSLICES 8 > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h > index adab4d2c29ac..81f9de45ab36 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h > @@ -16,6 +16,7 @@ > #include "uc/intel_uc.h" > > #include "i915_vma.h" > +#include "intel_engine_types.h" > #include "intel_reset_types.h" > #include "intel_wakeref.h" > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 14165d619175..827795262d68 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -272,30 +272,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) > #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) > > -/* Engine ID */ > - > -#define RCS0_HW 0 > -#define VCS0_HW 1 > -#define BCS0_HW 2 > -#define VECS0_HW 3 > -#define VCS1_HW 4 > -#define VCS2_HW 6 > -#define VCS3_HW 7 > -#define VECS1_HW 12 > - > -/* Engine class */ > - > -#define RENDER_CLASS 0 > -#define VIDEO_DECODE_CLASS 1 > -#define VIDEO_ENHANCEMENT_CLASS 2 > -#define COPY_ENGINE_CLASS 3 > -#define OTHER_CLASS 4 > -#define MAX_ENGINE_CLASS 4 > - > -#define OTHER_GUC_INSTANCE 0 > -#define OTHER_GTPM_INSTANCE 1 > -#define MAX_ENGINE_INSTANCE 3 > - > /* PCI config space */ > > #define MCHBAR_I915 0x44 > @@ -7505,6 +7481,9 @@ enum { > #define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16) > #define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20) > #define GEN11_INTR_ENGINE_INTR(x) ((x) & 0xffff) > +/* irq instances for OTHER_CLASS */ > +#define OTHER_GUC_INSTANCE 0 > +#define OTHER_GTPM_INSTANCE 1 > > #define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4)) > > -- > 2.22.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h index a0f372807dd4..8f10c5ffd68d 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_types.h +++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h @@ -26,6 +26,26 @@ #include "intel_wakeref.h" #include "intel_workarounds_types.h" +/* Legacy HW Engine ID */ + +#define RCS0_HW 0 +#define VCS0_HW 1 +#define BCS0_HW 2 +#define VECS0_HW 3 +#define VCS1_HW 4 +#define VCS2_HW 6 +#define VCS3_HW 7 +#define VECS1_HW 12 + +/* Gen11+ HW Engine class + instance */ +#define RENDER_CLASS 0 +#define VIDEO_DECODE_CLASS 1 +#define VIDEO_ENHANCEMENT_CLASS 2 +#define COPY_ENGINE_CLASS 3 +#define OTHER_CLASS 4 +#define MAX_ENGINE_CLASS 4 +#define MAX_ENGINE_INSTANCE 3 + #define I915_MAX_SLICES 3 #define I915_MAX_SUBSLICES 8 diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h index adab4d2c29ac..81f9de45ab36 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h @@ -16,6 +16,7 @@ #include "uc/intel_uc.h" #include "i915_vma.h" +#include "intel_engine_types.h" #include "intel_reset_types.h" #include "intel_wakeref.h" diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 14165d619175..827795262d68 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -272,30 +272,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); }) #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0)) -/* Engine ID */ - -#define RCS0_HW 0 -#define VCS0_HW 1 -#define BCS0_HW 2 -#define VECS0_HW 3 -#define VCS1_HW 4 -#define VCS2_HW 6 -#define VCS3_HW 7 -#define VECS1_HW 12 - -/* Engine class */ - -#define RENDER_CLASS 0 -#define VIDEO_DECODE_CLASS 1 -#define VIDEO_ENHANCEMENT_CLASS 2 -#define COPY_ENGINE_CLASS 3 -#define OTHER_CLASS 4 -#define MAX_ENGINE_CLASS 4 - -#define OTHER_GUC_INSTANCE 0 -#define OTHER_GTPM_INSTANCE 1 -#define MAX_ENGINE_INSTANCE 3 - /* PCI config space */ #define MCHBAR_I915 0x44 @@ -7505,6 +7481,9 @@ enum { #define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16) #define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20) #define GEN11_INTR_ENGINE_INTR(x) ((x) & 0xffff) +/* irq instances for OTHER_CLASS */ +#define OTHER_GUC_INSTANCE 0 +#define OTHER_GTPM_INSTANCE 1 #define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4))
To remove the dependency between the GT headers and i915_reg.h, move the definition of the engine IDs/classes to intel_engine_types.h Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> --- drivers/gpu/drm/i915/gt/intel_engine_types.h | 20 +++++++++++++++ drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 + drivers/gpu/drm/i915/i915_reg.h | 27 +++----------------- 3 files changed, 24 insertions(+), 24 deletions(-)