diff mbox series

[v2,07/40] drm/i915: Do not unmask PSR interruption in IRQ postinstall

Message ID 20190817093902.2171-8-lucas.demarchi@intel.com (mailing list archive)
State New, archived
Headers show
Series Tiger Lake batch 3 | expand

Commit Message

Lucas De Marchi Aug. 17, 2019, 9:38 a.m. UTC 
From: José Roberto de Souza <jose.souza@intel.com>

No need to unmask PSR interrutpion if PSR is not enabled, better move
the call to intel_psr_enable_source().

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 4 +++-
 drivers/gpu/drm/i915/display/intel_psr.h | 1 -
 drivers/gpu/drm/i915/i915_irq.c          | 2 --
 3 files changed, 3 insertions(+), 4 deletions(-)

Comments

Souza, Jose Aug. 20, 2019, 10:20 p.m. UTC | #1 
On Tue, 2019-08-20 at 13:29 -0700, Lucas De Marchi wrote:
> On Sat, Aug 17, 2019 at 02:38:29AM -0700, Lucas De Marchi wrote:
> > From: José Roberto de Souza <jose.souza@intel.com>
> > 
> > No need to unmask PSR interrutpion if PSR is not enabled, better
> > move
> > the call to intel_psr_enable_source().
> > 
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_psr.c | 4 +++-
> > drivers/gpu/drm/i915/display/intel_psr.h | 1 -
> > drivers/gpu/drm/i915/i915_irq.c          | 2 --
> > 3 files changed, 3 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 4353270bd65c..ecf945aef922 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -105,7 +105,7 @@ static int edp_psr_shift(enum transcoder
> > cpu_transcoder)
> > 	}
> > }
> > 
> > -void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32
> > debug)
> > +static void intel_psr_irq_control(struct drm_i915_private
> > *dev_priv, u32 debug)
> 
> intel_psr.c seems not to follow the convention of not using a prefix
> for
> static functions. But it would be nice to make it so, i.e.
> psr_irq_control().

Fair, will do that for this one

> 
> > {
> > 	u32 debug_mask, mask;
> > 	enum transcoder cpu_transcoder;
> > @@ -737,6 +737,8 @@ static void intel_psr_enable_source(struct
> > intel_dp *intel_dp,
> > 		mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
> > 
> > 	I915_WRITE(EDP_PSR_DEBUG(dev_priv->psr.transcoder), mask);
> > +
> > +	intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
> 
> shouldn't this be done before the other writes in this function?

The unmask of necessary interrupts only needs to be done before
intel_psr_activate()

> 
> Lucas De Marchi
> 
> > }
> > 
> > static void intel_psr_enable_locked(struct drm_i915_private
> > *dev_priv,
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > b/drivers/gpu/drm/i915/display/intel_psr.h
> > index dc818826f36d..46e4de8b8cd5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > @@ -30,7 +30,6 @@ void intel_psr_flush(struct drm_i915_private
> > *dev_priv,
> > void intel_psr_init(struct drm_i915_private *dev_priv);
> > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > 			      struct intel_crtc_state *crtc_state);
> > -void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32
> > debug);
> > void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32
> > psr_iir);
> > void intel_psr_short_pulse(struct intel_dp *intel_dp);
> > int intel_psr_wait_for_idle(const struct intel_crtc_state
> > *new_crtc_state,
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > b/drivers/gpu/drm/i915/i915_irq.c
> > index 37e3dd3c1a9d..77391d8325bf 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -3684,7 +3684,6 @@ static void ironlake_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> > 
> > 	if (IS_HASWELL(dev_priv)) {
> > 		gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
> > -		intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
> > 		display_mask |= DE_EDP_PSR_INT_HSW;
> > 	}
> > 
> > @@ -3795,7 +3794,6 @@ static void gen8_de_irq_postinstall(struct
> > drm_i915_private *dev_priv)
> > 		de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
> > 
> > 	gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
> > -	intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
> > 
> > 	for_each_pipe(dev_priv, pipe) {
> > 		dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
> > -- 
> > 2.21.0
> >
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 4353270bd65c..ecf945aef922 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -105,7 +105,7 @@  static int edp_psr_shift(enum transcoder cpu_transcoder)
 	}
 }
 
-void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug)
+static void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug)
 {
 	u32 debug_mask, mask;
 	enum transcoder cpu_transcoder;
@@ -737,6 +737,8 @@  static void intel_psr_enable_source(struct intel_dp *intel_dp,
 		mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE;
 
 	I915_WRITE(EDP_PSR_DEBUG(dev_priv->psr.transcoder), mask);
+
+	intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
 }
 
 static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index dc818826f36d..46e4de8b8cd5 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -30,7 +30,6 @@  void intel_psr_flush(struct drm_i915_private *dev_priv,
 void intel_psr_init(struct drm_i915_private *dev_priv);
 void intel_psr_compute_config(struct intel_dp *intel_dp,
 			      struct intel_crtc_state *crtc_state);
-void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug);
 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
 void intel_psr_short_pulse(struct intel_dp *intel_dp);
 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 37e3dd3c1a9d..77391d8325bf 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3684,7 +3684,6 @@  static void ironlake_irq_postinstall(struct drm_i915_private *dev_priv)
 
 	if (IS_HASWELL(dev_priv)) {
 		gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
-		intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
 		display_mask |= DE_EDP_PSR_INT_HSW;
 	}
 
@@ -3795,7 +3794,6 @@  static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 		de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
 
 	gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
-	intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
 
 	for_each_pipe(dev_priv, pipe) {
 		dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;