[v2] drm/i915/gen11: Add Wa_1604278689:icl,ehl
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Message ID 20190819180822.15665-1-matthew.d.roper@intel.com
State New
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Series
  • [v2] drm/i915/gen11: Add Wa_1604278689:icl,ehl
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Commit Message

Matt Roper Aug. 19, 2019, 6:08 p.m. UTC
From the bspec:

        "SW must always program the FBC_RT_BASE_ADDR_REGISTER_* register
        in Render Engine to a reserved value (0xFFFF_FFFF) such that the
        programmed value doesn’t match the render target surface address
        programmed. This would disable render engine from generating
        modify messages to FBC unit in display."

This workaround seems a bit questionable as written since using all 1's
to the RT_BASE register implies setting bit 0, which is a flag to
indicate whether the address is valid.  Indeed, we start seeing CI
failures when we follow the directions here literally.  Let's slightly
deviate from the workaround instructions and set all bits _except_ for
bit 0 of FBC_RT_BASE_ADDR_REGISTER.

v2:
 - Mask off the RT_VALID bit.  Experimentation with CI trybot indicates
   that this is necessary to avoid reset failures on BCS.

Bspec: 11388
Bspec: 33451
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
 drivers/gpu/drm/i915/i915_reg.h             | 1 +
 2 files changed, 7 insertions(+)

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 704ace01e7f5..f70b7a95bc23 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -567,6 +567,12 @@  static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 	/* allow headerless messages for preemptible GPGPU context */
 	WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE,
 			  GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
+
+	/* Wa_1604278689:icl,ehl */
+	wa_write_masked_or(wal, IVB_FBC_RT_BASE_UPPER,
+			   0, /* write-only register; skip validation */
+			   0xFFFFFFFF);
+	wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ea2f0fa2402d..bce7326329db 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3170,6 +3170,7 @@  static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 
 /* Framebuffer compression for Ivybridge */
 #define IVB_FBC_RT_BASE			_MMIO(0x7020)
+#define IVB_FBC_RT_BASE_UPPER		_MMIO(0x7024)
 
 #define IPS_CTL		_MMIO(0x43408)
 #define   IPS_ENABLE	(1 << 31)