[10/11] drm/i915: Add new function to copy subslices for a slice
diff mbox series

Message ID 20190820230544.170010-11-stuart.summers@intel.com
State New
Headers show
Series
  • Refactor to expand subslice mask (rev 2)
Related show

Commit Message

Summers, Stuart Aug. 20, 2019, 11:05 p.m. UTC
Add a new function to copy subslices for a specified slice
between intel_sseu structures for the purpose of determining
power-gate status.

Signed-off-by: Stuart Summers <stuart.summers@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 17 ++++++++++++++---
 1 file changed, 14 insertions(+), 3 deletions(-)

Comments

Chris Wilson Aug. 21, 2019, 10:41 p.m. UTC | #1
Quoting Stuart Summers (2019-08-21 00:05:43)
> Add a new function to copy subslices for a specified slice
> between intel_sseu structures for the purpose of determining
> power-gate status.

And ss_stride happens to be one in all cases so far?

For one hsw variant, it is 2 if I am not mistaken. But that isn't
converted.

Could you please drop a note saying that ss_stride is 1!

> Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Summers, Stuart Aug. 22, 2019, 4:36 p.m. UTC | #2
On Wed, 2019-08-21 at 23:41 +0100, Chris Wilson wrote:
> Quoting Stuart Summers (2019-08-21 00:05:43)
> > Add a new function to copy subslices for a specified slice
> > between intel_sseu structures for the purpose of determining
> > power-gate status.
> 
> And ss_stride happens to be one in all cases so far?

True.

> 
> For one hsw variant, it is 2 if I am not mistaken. But that isn't
> converted.

I believe this is for the eu stride, not the subslice stride. We have
the HSW_F1_EU_DIS_10EUS flag to represent this.

> 
> Could you please drop a note saying that ss_stride is 1!

No problem though. I'll add this to the commit message.

> 
> > Signed-off-by: Stuart Summers <stuart.summers@intel.com>
> 
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

Thanks!

-Stuart

Patch
diff mbox series

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 8c5eca72ff5e..e975cad03e39 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3721,6 +3721,15 @@  i915_cache_sharing_set(void *data, u64 val)
 	return 0;
 }
 
+static void
+intel_sseu_copy_subslices(const struct sseu_dev_info *sseu, int slice,
+			  u8 *to_mask)
+{
+	int offset = slice * sseu->ss_stride;
+
+	memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride);
+}
+
 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
 			i915_cache_sharing_get, i915_cache_sharing_set,
 			"%llu\n");
@@ -3794,7 +3803,7 @@  static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
 			continue;
 
 		sseu->slice_mask |= BIT(s);
-		sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
+		intel_sseu_copy_subslices(&info->sseu, s, sseu->subslice_mask);
 
 		for (ss = 0; ss < info->sseu.max_subslices; ss++) {
 			unsigned int eu_cnt;
@@ -3845,7 +3854,8 @@  static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
 		sseu->slice_mask |= BIT(s);
 
 		if (IS_GEN9_BC(dev_priv))
-			sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
+			intel_sseu_copy_subslices(&info->sseu, s,
+						  sseu->subslice_mask);
 
 		for (ss = 0; ss < info->sseu.max_subslices; ss++) {
 			unsigned int eu_cnt;
@@ -3881,7 +3891,8 @@  static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
 	if (sseu->slice_mask) {
 		sseu->eu_per_subslice = info->sseu.eu_per_subslice;
 		for (s = 0; s < fls(sseu->slice_mask); s++)
-			sseu->subslice_mask[s] = info->sseu.subslice_mask[s];
+			intel_sseu_copy_subslices(&info->sseu, s,
+						  sseu->subslice_mask);
 		sseu->eu_total = sseu->eu_per_subslice *
 				 intel_sseu_subslice_total(sseu);