From patchwork Wed Aug 21 03:23:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Xiong Y" X-Patchwork-Id: 11105287 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1C44614DE for ; Wed, 21 Aug 2019 03:18:23 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F077922DD3 for ; Wed, 21 Aug 2019 03:18:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F077922DD3 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 36E376E1B7; Wed, 21 Aug 2019 03:18:21 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3F50F6E1B2; Wed, 21 Aug 2019 03:18:20 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Aug 2019 20:18:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,410,1559545200"; d="scan'208";a="183397752" Received: from test-optiplex-7040.bj.intel.com ([10.238.154.166]) by orsmga006.jf.intel.com with ESMTP; 20 Aug 2019 20:18:17 -0700 From: Xiong Zhang To: intel-gfx@lists.freedesktop.org, intel-gvt-dev@lists.freedesktop.org Date: Wed, 21 Aug 2019 11:23:10 +0800 Message-Id: <1566357790-5003-1-git-send-email-xiong.y.zhang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1566279978-9659-2-git-send-email-xiong.y.zhang@intel.com> References: <1566279978-9659-2-git-send-email-xiong.y.zhang@intel.com> Subject: [Intel-gfx] [PATCH v2] drm/i915: Move vgpu balloon info into i915_virtual_gpu struct X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" vgpu ballon info consists of four drm_mm_node which is used to reserve ggtt space, then linux guest won't use these reserved ggtt space. Each vgpu has its own ballon info, so move ballon info into i915_virtual_gpu structure. v2: Fix dim PARENTHESIS_ALIGNMENT check warning Signed-off-by: Xiong Zhang Reviewed-by: Zhenyu Wang --- drivers/gpu/drm/i915/i915_drv.h | 14 ++++++++++++++ drivers/gpu/drm/i915/i915_vgpu.c | 40 +++++++++++++++++----------------------- 2 files changed, 31 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 18be8b2..9c14095 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1024,6 +1024,20 @@ struct i915_frontbuffer_tracking { struct i915_virtual_gpu { bool active; u32 caps; + + struct balloon_info { + /* + * There are up to 2 regions per mappable/unmappable graphic + * memory that might be ballooned. Here, index 0/1 is for + * mappable graphic memory, 2/3 for unmappable graphic memory. + */ +#define VGPU_MAPPABLE_BALLOON_LOW 0 +#define VGPU_MAPPABLE_BALLOON_HIGH 1 +#define VGPU_UNMAPPABLE_BALLOON_LOW 2 +#define VGPU_UNMAPPABLE_BALLOON_HIGH 3 +#define VGPU_MAX_BALLOON_NUM 4 + struct drm_mm_node space[VGPU_MAX_BALLOON_NUM]; + } bl_info; }; /* used in computing the new watermarks state */ diff --git a/drivers/gpu/drm/i915/i915_vgpu.c b/drivers/gpu/drm/i915/i915_vgpu.c index d2fd66f..0ed35f4 100644 --- a/drivers/gpu/drm/i915/i915_vgpu.c +++ b/drivers/gpu/drm/i915/i915_vgpu.c @@ -105,17 +105,6 @@ bool intel_vgpu_has_full_ppgtt(struct drm_i915_private *dev_priv) return dev_priv->vgpu.caps & VGT_CAPS_FULL_PPGTT; } -struct _balloon_info_ { - /* - * There are up to 2 regions per mappable/unmappable graphic - * memory that might be ballooned. Here, index 0/1 is for mappable - * graphic memory, 2/3 for unmappable graphic memory. - */ - struct drm_mm_node space[4]; -}; - -static struct _balloon_info_ bl_info; - static void vgt_deballoon_space(struct i915_ggtt *ggtt, struct drm_mm_node *node) { @@ -140,15 +129,16 @@ static void vgt_deballoon_space(struct i915_ggtt *ggtt, */ void intel_vgt_deballoon(struct i915_ggtt *ggtt) { + struct drm_i915_private *dev_priv = ggtt->vm.i915; int i; - if (!intel_vgpu_active(ggtt->vm.i915)) + if (!intel_vgpu_active(dev_priv)) return; DRM_DEBUG("VGT deballoon.\n"); - for (i = 0; i < 4; i++) - vgt_deballoon_space(ggtt, &bl_info.space[i]); + for (i = 0; i < VGPU_MAX_BALLOON_NUM; i++) + vgt_deballoon_space(ggtt, &dev_priv->vgpu.bl_info.space[i]); } static int vgt_balloon_space(struct i915_ggtt *ggtt, @@ -219,6 +209,7 @@ static int vgt_balloon_space(struct i915_ggtt *ggtt, int intel_vgt_balloon(struct i915_ggtt *ggtt) { struct intel_uncore *uncore = &ggtt->vm.i915->uncore; + struct drm_mm_node *space; unsigned long ggtt_end = ggtt->vm.total; unsigned long mappable_base, mappable_size, mappable_end; @@ -253,9 +244,11 @@ int intel_vgt_balloon(struct i915_ggtt *ggtt) return -EINVAL; } + space = ggtt->vm.i915->vgpu.bl_info.space; /* Unmappable graphic memory ballooning */ if (unmappable_base > ggtt->mappable_end) { - ret = vgt_balloon_space(ggtt, &bl_info.space[2], + ret = vgt_balloon_space(ggtt, + &space[VGPU_UNMAPPABLE_BALLOON_LOW], ggtt->mappable_end, unmappable_base); if (ret) @@ -263,7 +256,8 @@ int intel_vgt_balloon(struct i915_ggtt *ggtt) } if (unmappable_end < ggtt_end) { - ret = vgt_balloon_space(ggtt, &bl_info.space[3], + ret = vgt_balloon_space(ggtt, + &space[VGPU_UNMAPPABLE_BALLOON_HIGH], unmappable_end, ggtt_end); if (ret) goto err_upon_mappable; @@ -271,17 +265,17 @@ int intel_vgt_balloon(struct i915_ggtt *ggtt) /* Mappable graphic memory ballooning */ if (mappable_base) { - ret = vgt_balloon_space(ggtt, &bl_info.space[0], + ret = vgt_balloon_space(ggtt, + &space[VGPU_MAPPABLE_BALLOON_LOW], 0, mappable_base); - if (ret) goto err_upon_unmappable; } if (mappable_end < ggtt->mappable_end) { - ret = vgt_balloon_space(ggtt, &bl_info.space[1], + ret = vgt_balloon_space(ggtt, + &space[VGPU_MAPPABLE_BALLOON_HIGH], mappable_end, ggtt->mappable_end); - if (ret) goto err_below_mappable; } @@ -290,11 +284,11 @@ int intel_vgt_balloon(struct i915_ggtt *ggtt) return 0; err_below_mappable: - vgt_deballoon_space(ggtt, &bl_info.space[0]); + vgt_deballoon_space(ggtt, &space[VGPU_MAPPABLE_BALLOON_LOW]); err_upon_unmappable: - vgt_deballoon_space(ggtt, &bl_info.space[3]); + vgt_deballoon_space(ggtt, &space[VGPU_UNMAPPABLE_BALLOON_HIGH]); err_upon_mappable: - vgt_deballoon_space(ggtt, &bl_info.space[2]); + vgt_deballoon_space(ggtt, &space[VGPU_UNMAPPABLE_BALLOON_LOW]); err: DRM_ERROR("VGT balloon fail\n"); return ret;